Difference between revisions of "User:Tbenz"
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| + | =Thomas Benz= | ||
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| + | [[File:Tbenz_face_pulp_team.jpg|thumb|200px|]] | ||
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| + | I am currently pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. I completed my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2018 and 2020, respectively. | ||
| + | |||
| + | My interests include: | ||
| + | |||
| + | * Memory systems for high-performance Systems | ||
| + | * Energy-efficient high-performance SoCs | ||
| + | * Energy estimation and energy-aware scheduling in embedded systems | ||
| + | * Design, fabrication, and testing of application-specific integrated circuits | ||
| + | |||
| + | ==Contact== | ||
| + | |||
| + | * '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch] | ||
| + | * '''phone''': +41 44 632 05 18 | ||
| + | * '''office''': ETZ J85 | ||
| + | |||
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| + | ===Reserved Projects=== | ||
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| + | category = Reserved | ||
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Latest revision as of 21:08, 2 August 2022
Contents
Thomas Benz
I am currently pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. I completed my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2018 and 2020, respectively.
My interests include:
- Memory systems for high-performance Systems
- Energy-efficient high-performance SoCs
- Energy estimation and energy-aware scheduling in embedded systems
- Design, fabrication, and testing of application-specific integrated circuits
Contact
- e-mail: tbenz@iis.ee.ethz.ch
- phone: +41 44 632 05 18
- office: ETZ J85
Projects
Available Projects
- FPGA mapping of RPC DRAM
- Advanced Data Movers for Modern Neural Networks
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- IP-Based SoC Generation and Configuration (1-3S/B)
Projects In Progress
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
Completed Projects
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
