VLSI Implementation of a 5G Ciphering Accelerator
The Internet-of-Things promising to connect everything will enable many new applications in the realm of smart homes, smart cities, industry 4.0, or smart transportation just to name a few. Quite a few of these applications including cyber-physical systems and self-driving cars demand for reliable and secure communication links in order to avoid dangerous malfunctions or external attacks. 5G cellular networks counteract these challenges by standardizing an Ultra-Reliable Low-Latency Communication (URLLC) link using strong ciphering algorithms such as AES-128 and ZUC.
The goal of this project is to design an hardware-efficient ASIC supporting 5G ciphering algorithms for URLLC applications. After an initial phase focusing on the familiarization with ciphering algorithms, you will develop an efficient ciphering architecture meeting the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be derived by logic synthesis of the developed RTL code followed by a place-and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art.
- Looking for Interested Master Students (Semester Project / Master Thesis)
- Contact: Matthias Korb
- VLSI I
- 20% Theory, Algorithms, and Simulation
- 40% Architectural Design
- 40% HDL Implementation