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Difference between revisions of "VLSI Implementation of a 5G Ciphering Accelerator"

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[[File:5G-Security.jpg|thumb|400px|5G Security, Source: https://5g.security]]
 
[[File:5G-Security.jpg|thumb|400px|5G Security, Source: https://5g.security]]
 
==Short Description==
 
==Short Description==
Today, Turbo Decoder and LDPC Decoder are well established in the majority of communication systems. While the physical baseband computation in the cellular LTE standard bases for example on Turbo codes, LDPC codes have been adopted in the WiFi standard IEEE802.11n/ac/ax. With that the question arises: What comes next?
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The Internet-of-Things promising to connect everything will enable many new applications in the realm of smart homes, smart cities, industry 4.0, or smart transportation just to name a few. Quite a few of these applications including cyber-physical systems and self-driving cars demand for reliable and secure communication links in order to avoid dangerous malfunctions or external attacks. 5G cellular networks counteract these challenges by standardizing an Ultra-Reliable Low-Latency Communication (URLLC) link using strong ciphering algorithms such as AES-128 and ZUC.
  
 
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The goal of this project is to design an hardware-efficient ASIC supporting 5G ciphering algorithms for URLLC applications. After an initial phase focusing on the familiarization with ciphering algorithms, you will develop an efficient ciphering architecture meeting the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be derived by logic synthesis of the developed RTL code followed by a place-and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art.  
There are various channel decoding algorithms which could potentially succeed Turbo and LDPC codes. Promising candidates are: Non-binary LDPC codes, Spatially-Coupled LDPC Codes, and Polar Codes. The goal of this project is to do a quantitative evaluation of the channel decoding candidates based on optimized VLSI implementations.
 
 
 
 
 
Your first task in this project will be to develop a hardware-friendly decoder architecture for one of the channel decoder candidates. After porting the decoder architecture to HDL, an ASIC implementation will be derived by logic synthesis of the developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decoder candidates.
 
 
 
In case a Master Thesis is pursued, one further task will be to optimize the selected fix-point decoding algorithm towards a VLSI implementation.
 
  
 
===Status: Available ===
 
===Status: Available ===
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[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
 
[[Category:Hot]]
 
[[Category:Hot]]
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[[Category:Available]]
 
[[Category:ASIC]]
 
[[Category:ASIC]]
 
[[Category:Telecommunications]]
 
[[Category:Telecommunications]]

Revision as of 13:44, 13 November 2020

5G Security, Source: https://5g.security

Short Description

The Internet-of-Things promising to connect everything will enable many new applications in the realm of smart homes, smart cities, industry 4.0, or smart transportation just to name a few. Quite a few of these applications including cyber-physical systems and self-driving cars demand for reliable and secure communication links in order to avoid dangerous malfunctions or external attacks. 5G cellular networks counteract these challenges by standardizing an Ultra-Reliable Low-Latency Communication (URLLC) link using strong ciphering algorithms such as AES-128 and ZUC.

The goal of this project is to design an hardware-efficient ASIC supporting 5G ciphering algorithms for URLLC applications. After an initial phase focusing on the familiarization with ciphering algorithms, you will develop an efficient ciphering architecture meeting the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be derived by logic synthesis of the developed RTL code followed by a place-and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art.

Status: Available

Looking for Interested Master Students (Semester Project / Master Thesis)
Contact: Matthias Korb

Prerequisites

VLSI I

Character

20% Theory, Algorithms, and Simulation
40% Architectural Design
40% HDL Implementation

Professor

Qiuting Huang

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