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Difference between revisions of "WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing"

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==Introduction==
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==Abstract==
Mobile communication modems face the ever increasing challenge of multi-mode support. The times when a 2G cellular modem was a success are long past. Today, only SoCs with 2G/3G/4G, WiFi, and Bluetooth support seem to have a right to exist in the smart phone industry. On the other hand, power consumption requirements are ever more stringent and are hard to fulfill with simultaneous multi-mode support. One option to cope with this problem is the use of dedicated VLSI IP cores, one for each standard, in a complete SoC. During this project, the base for a 3G UMTS baseband core shall be laid.
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This thesis proposes a complete cell-search solution for real-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an inaccuracy of crystal oscillators within handsets and could cause fatal performance degradation.
  
==Project Description==
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A pipelined process of the code and time synchronization algorithm that minimizes the average code acquisition time, while keeping the complexity to a minimum, is considered. The effect of the frequency error (which may be as large as 30 kHz) on the initial cell search is marginalized by partial symbol despreading and non-coherent combining. Furthermore a coarse frequency
The overall goal of this project is to implement a 3G UMTS/HSPA+ modem in VLSI by reusing building blocks from other projects whenever possible. The Figure illustrates the modem setup consisting of
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estimation step where residual frequency error is reduced to a configurable amount (1 kHz is our value of choice) is implemented. Then a fine frequency estimation and tracking algorithm is designed utilizing a mapping of the closed form solution of the exponential sum problem within a closed-loop. This ensures a fine residual frequency offset less than 50 Hz.
* RF: up/down conversion, ADC/DAC, connect using RBDP [1] to signal processing blocks
 
* Digital Baseband Processing (DBB): synchronization, equalization, (de)modulation, channel (de)coding, connects to RF via data plane of RBDP
 
* Time Processing Unit (TPU): timing sensitive control of DBB, RF, and Power Amplifier (PA) via events and sequences, connects to RF via control plane of RBDP
 
* CPU: protocol stack software on top of a Real Time OS (RTOS), peripheral interconnect
 
  
Only the blue shaded part of the Figure shall be implemented during this project. This excludes peripherals such as SIM, Audio, and so on. As the implementation of the DBB would exceed the scope of a Master thesis only the cell search procedure shall be implemented. Furthermore, only rudimentary protocol stack software shall be written, just enough to hold a demonstration. The resulting system shall be demonstrated on an FPGA based testbed for fast prototyping and verification. A commercial RF hosted on the [[evaLTE]] FMC module provides analog functions.
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A series of fixed point simulations were conducted to minimize the circuit complexity. Further optimizations are considered in the design of hardware architecture and circuits to reduce the area and power consumption. The Digital Front End (DFE) is integrated with a Time Processing Unit (TPU) and a CPU along with the control logic to implement the digital part of a modem SoC. The entire DFE occupies a core area of 0.62 mm2 in a 1.2-V 0.13-μm CMOS technology with clock rate 76.8 MHz. Finally, to verify and demonstrate the cell search procedures, the developed modem is mapped to a Kintex 7 FPGA in conjunction with a commercial RF from ACP AG.
  
===Status: In Progress ===
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===Status: Completed ===
: Student: Taimir Aguacil (msc16f15)
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: Student: msc16f15
 
: Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Mkorb|Matthias Korb]], [[:User:Msalomon|Mauro Salomon]]
 
: Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Mkorb|Matthias Korb]], [[:User:Msalomon|Mauro Salomon]]
  
 
===Professor===
 
===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
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[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]
 
 
==References==
 
[1] Radio Front End - Baseband Digital Parallel (RBDP) Interface. https://www.jedec.org/standards-documents/docs/jesd-207, March 2007.
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]
[[Category:In progress]]
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[[Category:Completed]]
 
[[Category:Master Thesis]]
 
[[Category:Master Thesis]]
 
[[Category:FPGA]]
 
[[Category:FPGA]]

Latest revision as of 09:39, 6 November 2017

Aspired testbed setup with L2/L3 processing on PULP as well as dedicated DBB processing on an FPGA and RF on evaLTE FMC module.

Abstract

This thesis proposes a complete cell-search solution for real-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an inaccuracy of crystal oscillators within handsets and could cause fatal performance degradation.

A pipelined process of the code and time synchronization algorithm that minimizes the average code acquisition time, while keeping the complexity to a minimum, is considered. The effect of the frequency error (which may be as large as 30 kHz) on the initial cell search is marginalized by partial symbol despreading and non-coherent combining. Furthermore a coarse frequency estimation step where residual frequency error is reduced to a configurable amount (1 kHz is our value of choice) is implemented. Then a fine frequency estimation and tracking algorithm is designed utilizing a mapping of the closed form solution of the exponential sum problem within a closed-loop. This ensures a fine residual frequency offset less than 50 Hz.

A series of fixed point simulations were conducted to minimize the circuit complexity. Further optimizations are considered in the design of hardware architecture and circuits to reduce the area and power consumption. The Digital Front End (DFE) is integrated with a Time Processing Unit (TPU) and a CPU along with the control logic to implement the digital part of a modem SoC. The entire DFE occupies a core area of 0.62 mm2 in a 1.2-V 0.13-μm CMOS technology with clock rate 76.8 MHz. Finally, to verify and demonstrate the cell search procedures, the developed modem is mapped to a Kintex 7 FPGA in conjunction with a commercial RF from ACP AG.

Status: Completed

Student: msc16f15
Supervision: Benjamin Weber, Matthias Korb, Mauro Salomon

Professor

Qiuting Huang