http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Belfanti&feedformat=atomiis-projects - User contributions [en]2024-03-29T12:30:57ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Sandro_Belfanti&diff=2931Sandro Belfanti2017-08-17T15:04:19Z<p>Belfanti: /* Completed Projects */</p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
supresserrors = true<br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar or follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Turbo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
<br />
== Projects in Progress==<br />
<DynamicPageList><br />
supresserrors = true<br />
category = In progress<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
<br />
[[Category:Supervisors]]<br />
[[Category:Telecommunications]]<br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Sandro_Belfanti&diff=2930Sandro Belfanti2017-08-17T15:02:05Z<p>Belfanti: /* Completed Projects */</p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
supresserrors = true<br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar or follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
<br />
== Projects in Progress==<br />
<DynamicPageList><br />
supresserrors = true<br />
category = In progress<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
<br />
[[Category:Supervisors]]<br />
[[Category:Telecommunications]]<br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication&diff=2580Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication2016-12-29T14:13:56Z<p>Belfanti: /* Professor */</p>
<hr />
<div>[[File:Creating Bandwidth Extension with Carrier Aggregation.jpg|thumb|250px]]<br />
<br />
==Project no Longer Available==<br />
Please note that this project is no longer available.<br />
<br />
==Short Description==<br />
The future 4G mobile communication standard LTE-Advanced targets data rates in excess of 1Gbps in the downlink (base-station -> smartphone). These extremely high data rates can be achieved by transmitting over a wide RF band of up to 100MHz. Performing the A/D conversion for such a wide signal band is challenging. In addition, it appears very unlikely to have a continuous 100MHz-wide portion of the spectrum available. It is therefore desirable to split the spectrum into several smaller chunks, which are then combined in the digital front-end. This so called carrier aggregation is one of the most distinctive features of 4G mobile systems. In this project, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Advanced front-end and explore the impact of employing several parallel ADCs by using a behavioral model of a high performance ADC previously developed at the IIS. Finally, you will evaluate different strategies to improve the performance of this parallel bank of ADCs both in the digital and in the analog domain.<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB<br />
: Interest in mobile communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 60% MATLAB Implementation<br />
: 40% Simulation/Theory<br />
<br />
===Professor===<br />
<!--: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Telecommunications]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication&diff=2579Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication2016-12-29T14:13:44Z<p>Belfanti: /* Status: Available */</p>
<hr />
<div>[[File:Creating Bandwidth Extension with Carrier Aggregation.jpg|thumb|250px]]<br />
<br />
==Project no Longer Available==<br />
Please note that this project is no longer available.<br />
<br />
==Short Description==<br />
The future 4G mobile communication standard LTE-Advanced targets data rates in excess of 1Gbps in the downlink (base-station -> smartphone). These extremely high data rates can be achieved by transmitting over a wide RF band of up to 100MHz. Performing the A/D conversion for such a wide signal band is challenging. In addition, it appears very unlikely to have a continuous 100MHz-wide portion of the spectrum available. It is therefore desirable to split the spectrum into several smaller chunks, which are then combined in the digital front-end. This so called carrier aggregation is one of the most distinctive features of 4G mobile systems. In this project, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Advanced front-end and explore the impact of employing several parallel ADCs by using a behavioral model of a high performance ADC previously developed at the IIS. Finally, you will evaluate different strategies to improve the performance of this parallel bank of ADCs both in the digital and in the analog domain.<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB<br />
: Interest in mobile communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 60% MATLAB Implementation<br />
: 40% Simulation/Theory<br />
<br />
===Professor===<br />
<!--: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Telecommunications]]<br />
[[Category:Belfanti]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Non-binary_LDPC_Decoder_for_Deep-Space_Optical_Communications&diff=2228Non-binary LDPC Decoder for Deep-Space Optical Communications2016-07-21T14:05:51Z<p>Belfanti: </p>
<hr />
<div>==Short Description==<br />
Reliable wireless communication is always challenging, but especially so if one of the termials is located in deep space. In order to realize a communication link between a deep-space probe and a receiver on earth optical systems are currently being tested. A critical component in such a deep-space optical communication link is error correction, since the correct recovery of heavily attenuated signals is of utmost importance. In this project a non-binary LDPC code shall be examined for this purpose. The goal of this project is evaluating the performance of this code and developing an efficient decoding architecture. This project can be done as both, a semester or a master thesis. A semester project would focus mostly on simulation and evaluation and during a master project the complete decoder could be implemented and tested on an FPGA.<br />
<br />
===Status: Available after April 2016 ===<br />
: Looking for 1-2 Semester/Master students<br />
: Note that this project will have to start in April or May<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in communications / error correcting codes<br />
<br />
===Character===<br />
: 50% Theory/Simulation<br />
: 30% RTL Design<br />
: 20% VHDL Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Evaluation_Platform_for_Mobile_Communications&diff=2227An FPGA-Based Evaluation Platform for Mobile Communications2016-07-21T14:05:24Z<p>Belfanti: </p>
<hr />
<div>==Short Description==<br />
In this project you will implement a simulation environment for mobile communication receivers on an FPGA.<br />
<br />
==Description==<br />
<br />
All parts of a wireless receiver have to be carefully optimized in order to <br />
guarantee optimal performance. This is especially true for the word-widths<br />
of the signals in an implementation. Often, the word-width of every signal<br />
is individually tweaked for an optimal trade-off between performance loss and<br />
area and power consumption. However, this requires many time-consuming <br />
fixed-point simulations to make sure the performance loss is<br />
acceptable. <br />
<br />
In this project you will implement a simulation environment on a<br />
high-end FPGA board to speed up these simulations. The evaluation of<br />
communication algorithms (and decoders in particular) is always similar:<br />
+ Generate random data (bits)<br />
+ Code and modulate<br />
+ [optional: multipath channel]<br />
+ Add noise<br />
+ Receiver/Decoder (Model under Test)<br />
+ Calculate bit error rate (BER)<br />
All of this can be done on an FPGA, therefore greatly accelerating the<br />
simulation speed compared to a MATLAB-based implementation. The<br />
hardware model for the decoder ASIC can easily be transferred to an<br />
FPGA. The task of this project will be do implement the simulation<br />
environment on both the FPGA (random number generation, encoder and<br />
BER calculation) as well as on the PC (communication with the FPGA,<br />
plotting of the results). Several decoders have already been<br />
implemented in previous IIS projects and will be provided to test the setup.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
===Character===<br />
: 65% VHDL / FPGA implementation<br />
: 20% MATLAB implementation<br />
: 15% Testing<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:FPGA]]<br />
[[Category:Telecommunications]]<br />
[[Category:Belfanti]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=3D_Turbo_Decoder_ASIC_Realization&diff=21533D Turbo Decoder ASIC Realization2016-04-15T10:33:50Z<p>Belfanti: </p>
<hr />
<div>[[File:Creating 3D Turbo Codes.jpg|thumb|230px]]<br />
==Short Description==<br />
[[File:3DTurbo.png|thumb|A 3D turbo decoder layout of a previous project]]<br />
Reliable transmission of information despite unfavorable circumstances is the basis of digital communication. In order to provide good quality of service and high throughput powerful coding schemes are required in almost any application. Turbo codes offer outstanding error correction capabilities combined with efficient hardware architectures, which made them the method of choice in a great variety of applications ranging from 3G/4G cellular networks to satellite communications. Recently a new class of Turbo codes has been proposed, which can improve the error rate even further. Finding an efficient implementation for these 3D-Turbo codes will be your task during this thesis. You will start by evaluating the performance compared to the regular Turbo codes in MATLAB, then design a suitable architecture in order to arrive at a highly efficient VHDL implementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology.<br />
<br />
===Status: Completed ===<br />
<!--: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 30% Theory/Simulation<br />
: 50% VHDL<br />
: 20% ASIC Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Completed]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Signal_to_Noise_Ratio_Estimation_for_3G_standards&diff=2066Signal to Noise Ratio Estimation for 3G standards2016-04-14T09:23:24Z<p>Belfanti: </p>
<hr />
<div><!--[[File:Testbed.jpg|thumb|230px]]---><br />
==Short Description==<br />
In mobile communications, such as in the latest 3G standards, mobile phones usually operate in unfavorable environments. There is no line of sight, the base station is far away and other mobiles are interfering. Despite that we expect a reliable, error-free and fast connection. To achieve this goal and to combat all these negative influences we need to know the amount of noise in relation to the desired signal. This so-called signal-to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver.<br />
<br />
In this semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as a chip-design project, where an ASIC will be taped out and measured during the VLSI III lecture.<br />
<br />
===Status: No longer Available ===<br />
<!--: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Theory/Simulation<br />
: 50% VHDL<br />
: 30% ASIC Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Time_Synchronization_for_3G_Mobile_Communications&diff=2065Time Synchronization for 3G Mobile Communications2016-04-14T09:22:20Z<p>Belfanti: </p>
<hr />
<div><!--[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]]---><br />
==Short Description==<br />
Setting up the communication link between a mobile phone and the base station is no trivial task. Initially the mobile does not know anything about the base-station. <br />
It does not know when the different frames start, what cells are around and which synchronization codes are used. Solving this problem in dedicated hardware will be the<br />
topic of this thesis. Synchronization in time will detect the position of the frame boundaries and reveal the Cell ID of the strongest cell.<br />
This has to be implemented in hardware, and it is the very first task which is done to for the cellular communication. <br />
There are two options for this project. If you are interested in doing a chip design project for the VLSI lectures, you will implement the time synchronization in VHDL, synthesize it, perform the back-end and finally produce an ASIC. On the other hand, if you prefer working with FPGAs, you can alternatively implement the algorithm on an FPGA and test it in real-time and with real data on our 3G testbed.<br />
<br />
===Status: No Longer Available ===<br />
<!--: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 20% Theory/MATLAB<br />
: 30% VHDL<br />
: 50% Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
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COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
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[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Channel_Estimation_and_Equalization_for_LTE_Advanced&diff=2064Channel Estimation and Equalization for LTE Advanced2016-04-14T09:13:52Z<p>Belfanti: </p>
<hr />
<div>[[File:Channel Estimation and Equalization for LTE Advanced.jpg|thumb|400px]]<br />
==Short Description==<br />
LTE Advanced, the latest 4G mobile communications standard, will provide data rates of up to 3Gbps. It employs OFDM as a highly effective way to deal with frequency selective channels. For optimal performance an accurate channel estimation is crucial to reconstruct the transmitted symbols. Your task will be the development and hardware implementation of a channel estimator and equalizer for LTE Advanced. You will compare existing algorithms in MATLAB and come up with an efficient solution suitable for hardware implementation. <br />
<br />
Depending on your preferences you can the either start working on a novel algorithm in MATLAB or you implement your solution in VHDL, perform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into the most advanced mobile communications standard (LTE Advanced), OFDM, channel estimation algorithms, as well as VLSI design.<br />
<br />
===Status: No Longer Available ===<br />
<br />
<!-- <br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 50% VHDL<br />
: 30% Simulation/Theory<br />
: 20% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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GROUP<br />
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[[Category:Analog]]<br />
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<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
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TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
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NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_High-Throughput_Next_Generation_Turbo_Decoders&diff=2063ASIC Implementation of High-Throughput Next Generation Turbo Decoders2016-04-14T09:12:31Z<p>Belfanti: </p>
<hr />
<div>[[File:Creating 3D Turbo Codes.jpg|thumb|230px]]<br />
==Short Description==<br />
Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile communications, most modern systems rely on turbo codes because of their outstanding error correction capabilities in conjunction with efficient decoder implementations. For the most recently developed standards with throughput requirements in excess of 1Gbps, providing the necessary throughput has become a real challenge. The IIS has a long history of high-throughput turbo decoders and we have recently had several new ideas on how to improve our architectures even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, you can rely on the expertise from a long line of previous turbo decoders to hopefully develop an outstanding ASIC.<br />
<br />
If you are interested in doing a thesis (semester or master) in the field of error correcting codes, such as turbo codes, just contact [[:User:Belfanti |Sandro Belfanti]] or [[:User:rothc |Christoph Roth]]. There are different projects available, ranging from more theoretical/simulation based projects to the VLSI implementation in form of chip design projects.<br />
<br />
==Previous Turbo Decoders==<br />
[[File:Jetfire2sml overlay white.png|thumb|Turbo decoder ASIC previously fabricated at the IIS]]<br />
All the chips which have been fabricated can be found in the [http://asic.ethz.ch/cg/ IIS chip gallery]. Some examples for turbo decoders designed at the IIS are<br />
<br />
[http://asic.ethz.ch/cg/2010/LaLe.html LaLe: Turbo Decoder for TD-HSPA]<br />
<br />
[http://asic.ethz.ch/cg/2009/LTEturbo.html LTE-Turbo: Turbo Decoder for LTE]<br />
<br />
[http://asic.ethz.ch/cg/2012/Jetfire.html Jetfire: Turbo Decoder for LTE-Advanced]<br />
<!-- <br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
---><br />
===Status: Completed ===<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Simulation/Theory<br />
: 50% VHDL<br />
: 30% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Completed]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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[[Category:Analog]]<br />
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<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
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[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Digital_Transmitter_for_Mobile_Communications&diff=2062Digital Transmitter for Mobile Communications2016-04-14T09:11:35Z<p>Belfanti: </p>
<hr />
<div>[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]]<br />
==Short Description==<br />
In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the transceiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. <br />
The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver. <br />
<br />
The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a protocol tester and you will then be able to actually send data over the air.<br />
<br />
This project will give you insight into all parts of a modern 3G standard, such a coding, rate-matching, mapping and the digital frontend.<br />
<br />
===Status: Completed ===<br />
<!--===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 20% Theory/MATLAB<br />
: 30% VHDL<br />
: 50% Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Completed]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
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<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
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TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=FPGA-Based_Digital_Frontend_for_3G_Receivers&diff=2061FPGA-Based Digital Frontend for 3G Receivers2016-04-14T09:10:15Z<p>Belfanti: </p>
<hr />
<div>[[File:Testbed.JPG|thumb|230px]]<br />
==Short Description==<br />
A modern receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received data. <br />
In this project you will work on the very first digital block after the analog part. The received data has to be obtained from the analog frontend, filtered, down-sampled and non-idealities in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).<br />
A complete model of the digital receiver without the DFE has already been developed at the IIS. <br />
In order to work with real data this DFE will be implemented on a FPGA-board, which is connected to an existing analog tranceiver.<br />
Your task will be to implement the DFE on an FPGA and verify the functionality together with the already existing parts.<br />
In the end, the complete chain will be able to receive data which was generated by a protocol tester, transmitted over the air through analog frontend your DFE and the IIS digital baseband receiver.<br />
<br />
This project can either be varied and be done as either a semester or masters thesis.<br />
<br />
===Status: Completed ===<br />
<!--<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
---><br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Theory/Simulation<br />
: 50% VHDL<br />
: 30% FPGA Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Completed]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=4th_Generation_Synchronization&diff=20584th Generation Synchronization2016-04-14T09:08:34Z<p>Belfanti: </p>
<hr />
<div>[[File:LTE Synchronization.png|thumb]]<br />
<br />
==Short Description==<br />
Wireless communication imposes immense challenges on receiver design<br />
in case the transmitter and receiver are not synchronized. Strongly<br />
centralized network topologies such as cellular communication networks<br />
rely on high-quality hardware at the base transceiver station<br />
(BTS). This allows the network to be in sync with a common external<br />
signal (such as GPS). On the Mobile Station (MS) side, however, it<br />
cannot be guaranteed that such an external common clock signal is<br />
available at all times. Therefore, the BTS transmits synchronization<br />
data which allows the MS to synchronize in time and frequency to its<br />
serving BTS. Each cellular standard (GSM, UMTS, LTE) has its own set<br />
of synchronization signals.<br />
<br />
LTE synchronization consists of 4 parts [1-5]:<br />
# LTE center frequency detection.<br />
# OFDM symbol timing and fractional frequency offset detection.<br />
# LTE specific Primary Synchronization Sequence (PSS) detection.<br />
# LTE specific Secondary Synchronization Sequence (SSS) detection.<br />
A Matlab model performing above detection exists. During this project, the student is asked to find a suitable ASIC architecture for LTE synchronization, implement it, and send a chip to fabrication. The fabricated chip can then be tested on a commercial chip tester.<br />
<br />
===Status: Available ===<br />
: Looking for interested students (Semester or Master Thesis)<br />
: Supervision: [[:User:Weberbe|Benjamin Weber]]<br />
<br />
===Character===<br />
: 10% Theory<br />
: 60% Architecture design<br />
: 30% Implementation<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<br />
==References==<br />
[1] K. Manolakis, D.M. Gutierrez Estevez, V. Jungnickel, W. Xu, and C. Drewes. A Closed Concept for Synchronization and Cell Search in 3GPP LTE Systems. In ''Wireless Communications and Networking Conference'', 2009. WCNC 2009. IEEE, pages 1–6, April 2009.<br />
<br />
[2] W. Xu and K. Manolakis. Robust Synchronization for 3GPP LTE Systems. In ''Global Telecommunications Conference (GLOBECOM 2010)'', 2010 IEEE, pages 1–5, Dec 2010.<br />
<br />
[3] Jung-In Kim, Jung-Su Han, Hee-Jin Roh, and Hyung-Jin Choi. SSS Detection Method for Initial Cell Search in 3GPP LTE FDD/TDD Dual Mode Receiver. In ''Communications and Information Technology'', 2009. ISCIT 2009. 9th International Symposium on, pages 199–203, Sept 2009.<br />
<br />
[4] H. Xu, R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/028,674.<br />
<br />
[5] T. Erpek, K. Steadman, R. Krishnan, and Qiao Chen. LTE Signal Classification and Center Frequency Detection Without Priori Information. In ''Dynamic Spectrum Access Networks (DYSPAN)'', 2012 IEEE International Symposium on, pages 299–304, Oct 2012.<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Weberbe]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=4th_Generation_Synchronization&diff=20574th Generation Synchronization2016-04-14T09:08:04Z<p>Belfanti: /* Status: Available */</p>
<hr />
<div>[[File:LTE Synchronization.png|thumb]]<br />
<br />
==Short Description==<br />
Wireless communication imposes immense challenges on receiver design<br />
in case the transmitter and receiver are not synchronized. Strongly<br />
centralized network topologies such as cellular communication networks<br />
rely on high-quality hardware at the base transceiver station<br />
(BTS). This allows the network to be in sync with a common external<br />
signal (such as GPS). On the Mobile Station (MS) side, however, it<br />
cannot be guaranteed that such an external common clock signal is<br />
available at all times. Therefore, the BTS transmits synchronization<br />
data which allows the MS to synchronize in time and frequency to its<br />
serving BTS. Each cellular standard (GSM, UMTS, LTE) has its own set<br />
of synchronization signals.<br />
<br />
LTE synchronization consists of 4 parts [1-5]:<br />
# LTE center frequency detection.<br />
# OFDM symbol timing and fractional frequency offset detection.<br />
# LTE specific Primary Synchronization Sequence (PSS) detection.<br />
# LTE specific Secondary Synchronization Sequence (SSS) detection.<br />
A Matlab model performing above detection exists. During this project, the student is asked to find a suitable ASIC architecture for LTE synchronization, implement it, and send a chip to fabrication. The fabricated chip can then be tested on a commercial chip tester.<br />
<br />
===Status: Available ===<br />
: Looking for interested students (Semester or Master Thesis)<br />
: Supervision: [[:User:Weberbe|Benjamin Weber]]<br />
<br />
===Character===<br />
: 10% Theory<br />
: 60% Architecture design<br />
: 30% Implementation<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<br />
==References==<br />
[1] K. Manolakis, D.M. Gutierrez Estevez, V. Jungnickel, W. Xu, and C. Drewes. A Closed Concept for Synchronization and Cell Search in 3GPP LTE Systems. In ''Wireless Communications and Networking Conference'', 2009. WCNC 2009. IEEE, pages 1–6, April 2009.<br />
<br />
[2] W. Xu and K. Manolakis. Robust Synchronization for 3GPP LTE Systems. In ''Global Telecommunications Conference (GLOBECOM 2010)'', 2010 IEEE, pages 1–5, Dec 2010.<br />
<br />
[3] Jung-In Kim, Jung-Su Han, Hee-Jin Roh, and Hyung-Jin Choi. SSS Detection Method for Initial Cell Search in 3GPP LTE FDD/TDD Dual Mode Receiver. In ''Communications and Information Technology'', 2009. ISCIT 2009. 9th International Symposium on, pages 199–203, Sept 2009.<br />
<br />
[4] H. Xu, R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/028,674.<br />
<br />
[5] T. Erpek, K. Steadman, R. Krishnan, and Qiao Chen. LTE Signal Classification and Center Frequency Detection Without Priori Information. In ''Dynamic Spectrum Access Networks (DYSPAN)'', 2012 IEEE International Symposium on, pages 299–304, Oct 2012.<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Weberbe]]<br />
[[Category:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Non-binary_LDPC_Decoder_for_Deep-Space_Optical_Communications&diff=1981Non-binary LDPC Decoder for Deep-Space Optical Communications2016-03-03T15:42:33Z<p>Belfanti: /* Short Description */</p>
<hr />
<div>==Short Description==<br />
Reliable wireless communication is always challenging, but especially so if one of the termials is located in deep space. In order to realize a communication link between a deep-space probe and a receiver on earth optical systems are currently being tested. A critical component in such a deep-space optical communication link is error correction, since the correct recovery of heavily attenuated signals is of utmost importance. In this project a non-binary LDPC code shall be examined for this purpose. The goal of this project is evaluating the performance of this code and developing an efficient decoding architecture. This project can be done as both, a semester or a master thesis. A semester project would focus mostly on simulation and evaluation and during a master project the complete decoder could be implemented and tested on an FPGA.<br />
<br />
===Status: Available after April 2016 ===<br />
: Looking for 1-2 Semester/Master students<br />
: Note that this project will have to start in April or May<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in communications / error correcting codes<br />
<br />
===Character===<br />
: 50% Theory/Simulation<br />
: 30% RTL Design<br />
: 20% VHDL Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Hot]]<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Non-binary_LDPC_Decoder_for_Deep-Space_Optical_Communications&diff=1980Non-binary LDPC Decoder for Deep-Space Optical Communications2016-03-02T17:14:19Z<p>Belfanti: /* Short Description */</p>
<hr />
<div>==Short Description==<br />
Reliable wireless communication is always challenging, but especially so if one of the termials is located in deep space. In order to realize a communication link between a deep-space probe and a receiver on earth optical systems are currently being tested. A critical component in such a deep-space optical communication link is error correction, since the correct recovery of heavily attenuated signals is of utmost importance. In this project a non-binary LDPC code shall be examined for this purpose. The goal of this project is evaluating the performance of this code and developing an efficient decoding architecture. This project can be done as both, a semester or a master thesis. A semester project would focus mostly on simulation and evaluation and during a master project the complete decoder could be implemented and tested on an FPGA.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in communications / error correcting codes<br />
<br />
===Character===<br />
: 50% Theory/Simulation<br />
: 30% RTL Design<br />
: 20% VHDL Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Hot]]<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=3D_Turbo_Decoder_ASIC_Realization&diff=19613D Turbo Decoder ASIC Realization2016-02-19T09:27:21Z<p>Belfanti: Removed the HOT tag (moved it to the deep space optical communications project)</p>
<hr />
<div>[[File:Creating 3D Turbo Codes.jpg|thumb|230px]]<br />
==Short Description==<br />
[[File:3DTurbo.png|thumb|A 3D turbo decoder layout of a previous project]]<br />
Reliable transmission of information despite unfavorable circumstances is the basis of digital communication. In order to provide good quality of service and high throughput powerful coding schemes are required in almost any application. Turbo codes offer outstanding error correction capabilities combined with efficient hardware architectures, which made them the method of choice in a great variety of applications ranging from 3G/4G cellular networks to satellite communications. Recently a new class of Turbo codes has been proposed, which can improve the error rate even further. Finding an efficient implementation for these 3D-Turbo codes will be your task during this thesis. You will start by evaluating the performance compared to the regular Turbo codes in MATLAB, then design a suitable architecture in order to arrive at a highly efficient VHDL implementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 30% Theory/Simulation<br />
: 50% VHDL<br />
: 20% ASIC Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
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NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Non-binary_LDPC_Decoder_for_Deep-Space_Optical_Communications&diff=1960Non-binary LDPC Decoder for Deep-Space Optical Communications2016-02-19T09:26:10Z<p>Belfanti: Created page with "==Short Description== Reliable wireless communication is always challenging, but especially so if one of the termials is located in deep space. In order to realize a communica..."</p>
<hr />
<div>==Short Description==<br />
Reliable wireless communication is always challenging, but especially so if one of the termials is located in deep space. In order to realize a communication link between a deep-space probe and a receiver on earth optical systems are currently being tested. A critical component in such a deep-space optical communication link is error correction, since the correct recovery of heavily attenuated signals is of utmost importance. In this project a non-binary LDPC code shall be examined for this purpose. The goal of this project is evaluating the performance of this code and developing an efficient decoding architecture.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in communications / error correcting codes<br />
<br />
===Character===<br />
: 50% Theory/Simulation<br />
: 30% RTL Design<br />
: 20% VHDL Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Hot]]<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Sandro_Belfanti&diff=1596Sandro Belfanti2015-07-29T10:40:52Z<p>Belfanti: /* Available Projects */</p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
supresserrors = true<br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar or follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
<br />
== Projects in Progress==<br />
<DynamicPageList><br />
supresserrors = true<br />
category = In progress<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
<br />
[[Category:Supervisors]]<br />
[[Category:Telecommunications]]<br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Time_Synchronization_for_3G_Mobile_Communications&diff=1412Time Synchronization for 3G Mobile Communications2015-03-26T16:01:13Z<p>Belfanti: Created page with "<!--300px---> ==Short Description== Setting up the communication link between a mobile phone and t..."</p>
<hr />
<div><!--[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]]---><br />
==Short Description==<br />
Setting up the communication link between a mobile phone and the base station is no trivial task. Initially the mobile does not know anything about the base-station. <br />
It does not know when the different frames start, what cells are around and which synchronization codes are used. Solving this problem in dedicated hardware will be the<br />
topic of this thesis. Synchronization in time will detect the position of the frame boundaries and reveal the Cell ID of the strongest cell.<br />
This has to be implemented in hardware, and it is the very first task which is done to for the cellular communication. <br />
There are two options for this project. If you are interested in doing a chip design project for the VLSI lectures, you will implement the time synchronization in VHDL, synthesize it, perform the back-end and finally produce an ASIC. On the other hand, if you prefer working with FPGAs, you can alternatively implement the algorithm on an FPGA and test it in real-time and with real data on our 3G testbed.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 20% Theory/MATLAB<br />
: 30% VHDL<br />
: 50% Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
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COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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GROUP<br />
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[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Signal_to_Noise_Ratio_Estimation_for_3G_standards&diff=1305Signal to Noise Ratio Estimation for 3G standards2015-03-20T16:01:03Z<p>Belfanti: </p>
<hr />
<div><!--[[File:Testbed.jpg|thumb|230px]]---><br />
==Short Description==<br />
In mobile communications, such as in the latest 3G standards, mobile phones usually operate in unfavorable environments. There is no line of sight, the base station is far away and other mobiles are interfering. Despite that we expect a reliable, error-free and fast connection. To achieve this goal and to combat all these negative influences we need to know the amount of noise in relation to the desired signal. This so-called signal-to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver.<br />
<br />
In this semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as a chip-design project, where an ASIC will be taped out and measured during the VLSI III lecture.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Theory/Simulation<br />
: 50% VHDL<br />
: 30% ASIC Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Signal_to_Noise_Ratio_Estimation_for_3G_standards&diff=1304Signal to Noise Ratio Estimation for 3G standards2015-03-20T16:00:23Z<p>Belfanti: Created page with "230px ==Short Description== In mobile communications, such as in the latest 3G standards, mobile phones usually operate in unfavorable environments...."</p>
<hr />
<div>[[File:Testbed.jpg|thumb|230px]]<br />
==Short Description==<br />
In mobile communications, such as in the latest 3G standards, mobile phones usually operate in unfavorable environments. There is no line of sight, the base station is far away and other mobiles are interfering. Despite that we expect a reliable, error-free and fast connection. To achieve this goal and to combat all these negative influences we need to know the amount of noise in relation to the desired signal. This so-called signal-to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver.<br />
<br />
In this semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as a chip-design project, where an ASIC will be taped out and measured during the VLSI III lecture.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Theory/Simulation<br />
: 50% VHDL<br />
: 30% ASIC Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Belfanti]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication&diff=1302Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication2015-03-20T15:43:00Z<p>Belfanti: </p>
<hr />
<div>[[File:Creating Bandwidth Extension with Carrier Aggregation.jpg|thumb|250px]]<br />
<br />
==Project no Longer Available==<br />
Please note that this project is no longer available.<br />
<br />
==Short Description==<br />
The future 4G mobile communication standard LTE-Advanced targets data rates in excess of 1Gbps in the downlink (base-station -> smartphone). These extremely high data rates can be achieved by transmitting over a wide RF band of up to 100MHz. Performing the A/D conversion for such a wide signal band is challenging. In addition, it appears very unlikely to have a continuous 100MHz-wide portion of the spectrum available. It is therefore desirable to split the spectrum into several smaller chunks, which are then combined in the digital front-end. This so called carrier aggregation is one of the most distinctive features of 4G mobile systems. In this project, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Advanced front-end and explore the impact of employing several parallel ADCs by using a behavioral model of a high performance ADC previously developed at the IIS. Finally, you will evaluate different strategies to improve the performance of this parallel bank of ADCs both in the digital and in the analog domain.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB<br />
: Interest in mobile communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 60% MATLAB Implementation<br />
: 40% Simulation/Theory<br />
<br />
===Professor===<br />
<!--: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Telecommunications]]<br />
[[Category:Belfanti]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Testbed_for_3G_Mobile_Communications_Receivers&diff=1294An FPGA-Based Testbed for 3G Mobile Communications Receivers2015-03-11T10:31:50Z<p>Belfanti: /* Status: In Progress */</p>
<hr />
<div>[[File:Testbed.JPG|thumb|230px]]<br />
==Short Description==<br />
In this project you will develop and FPGA-based testbed for the 3G<br />
standard TD-SCDMA, with the option to extend it with an ASIC in the<br />
future. The digital baseband receiver already exists at the IIS, although without any realistic<br />
interfaces to frontend and higher layers. These interfaces will be<br />
written as part of this project.<br />
The goal is to map the existing receiver ASIC to an FPGA and devise <br />
a testbed including the analog frontend (which will be provided) as well as <br />
a micro controller board for easy access from a PC. <br />
To that end the existing receiver has to be extended to include a <br />
digital frontend as well as means to communicate with the micro controller.<br />
<br />
===Status: In Progress ===<br />
: Supervision: [[:User:Belfanti | Sandro Belfanti]], [[:User:Weberbe|Benjamin Weber]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:In progress]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Sandro_Belfanti&diff=1293Sandro Belfanti2015-03-11T10:30:39Z<p>Belfanti: /* Projects in Progress */</p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something in with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
supresserrors = true<br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar or follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
<br />
== Projects in Progress==<br />
<DynamicPageList><br />
supresserrors = true<br />
category = In progress<br />
category = Belfanti<br />
</DynamicPageList><br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
<br />
[[Category:Supervisors]]<br />
[[Category:Telecommunications]]<br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Testbed_for_3G_Mobile_Communications_Receivers&diff=1292An FPGA-Based Testbed for 3G Mobile Communications Receivers2015-03-10T16:53:39Z<p>Belfanti: Created page with "230px ==Short Description== In this project you will develop and FPGA-based testbed for the 3G standard TD-SCDMA, with the option to extend it with ..."</p>
<hr />
<div>[[File:Testbed.JPG|thumb|230px]]<br />
==Short Description==<br />
In this project you will develop and FPGA-based testbed for the 3G<br />
standard TD-SCDMA, with the option to extend it with an ASIC in the<br />
future. The digital baseband receiver already exists at the IIS, although without any realistic<br />
interfaces to frontend and higher layers. These interfaces will be<br />
written as part of this project.<br />
The goal is to map the existing receiver ASIC to an FPGA and devise <br />
a testbed including the analog frontend (which will be provided) as well as <br />
a micro controller board for easy access from a PC. <br />
To that end the existing receiver has to be extended to include a <br />
digital frontend as well as means to communicate with the micro controller.<br />
<br />
===Status: In Progress ===<br />
: Supervision: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:In progress]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Belfanti&diff=938Category:Belfanti2015-02-04T10:20:55Z<p>Belfanti: Redirected page to Sandro Belfanti</p>
<hr />
<div>#REDIRECT [[Sandro Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=User:Belfanti&diff=937User:Belfanti2015-02-04T10:20:24Z<p>Belfanti: Redirected page to Sandro Belfanti</p>
<hr />
<div>#REDIRECT [[Sandro Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Belfanti&diff=936Category:Belfanti2015-02-04T10:19:45Z<p>Belfanti: Redirected page to User:Belfanti</p>
<hr />
<div>#REDIRECT [[User:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Sandro_Belfanti&diff=935Sandro Belfanti2015-02-04T10:18:36Z<p>Belfanti: Created page with "==Sandro Belfanti== Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich,..."</p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something in with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
* [[Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication|Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication]]<br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar of follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
<br />
== Projects in Progress==<br />
<br />
<br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
[[Category:Supervisors]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=User:Belfanti&diff=934User:Belfanti2015-02-04T10:18:31Z<p>Belfanti: Redirected page to User:Belfanti</p>
<hr />
<div>#REDIRECT [[User:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Belfanti&diff=933Belfanti2015-02-04T10:17:43Z<p>Belfanti: Redirected page to User:Belfanti</p>
<hr />
<div>#REDIRECT [[User:Belfanti]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Telecommunications&diff=927Category:Telecommunications2015-02-04T09:37:08Z<p>Belfanti: /* Supervisors */</p>
<hr />
<div>==Telecommunications==<br />
<br />
<br />
==Supervisors==<br />
The following supervisors work in the field of telecommunications. Feel free to contact them if you want to do a project in this field.<br />
<br />
: [[:User:Belfanti | Sandro Belfanti]]<br />
: [[:User:Badawi | Karim Badawi]]<br />
: [[:User:Kroell| Harald Kröll]]<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/weberbe.en.html Benjamin Weber]<br />
<br />
==Active Projects==<br />
These are the projects that are currently active<br />
<DynamicPageList><br />
category = In progress<br />
category = Telecommunications<br />
</DynamicPageList><br />
---><br />
<br />
<br />
==Available Projects==<br />
We are still looking for students/partners to work on the following projects<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Telecommunications<br />
</DynamicPageList></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Telecommunications&diff=926Category:Telecommunications2015-02-04T09:36:58Z<p>Belfanti: /* Supervisors */</p>
<hr />
<div>==Telecommunications==<br />
<br />
<br />
==Supervisors==<br />
The following supervisors work in the field of telecommunications. Feel free to contact them if you want to do a project in this field.<br />
<br />
: [[:User:Belfanti | Sandro Belfanti]]<br />
: [[:User:Badawi | Karim Badawi]<br />
: [[:User:Kroell| Harald Kröll]]<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/weberbe.en.html Benjamin Weber]<br />
<br />
==Active Projects==<br />
These are the projects that are currently active<br />
<DynamicPageList><br />
category = In progress<br />
category = Telecommunications<br />
</DynamicPageList><br />
---><br />
<br />
<br />
==Available Projects==<br />
We are still looking for students/partners to work on the following projects<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Telecommunications<br />
</DynamicPageList></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Telecommunications&diff=925Category:Telecommunications2015-02-04T09:35:48Z<p>Belfanti: </p>
<hr />
<div>==Telecommunications==<br />
<br />
<br />
==Supervisors==<br />
The following supervisors work in the field of telecommunications. Feel free to contact them if you want to do a project in this field.<br />
<br />
[[:User:Belfanti | Sandro Belfanti]]<br />
[http://iis-projects.ee.ethz.ch/index.php/User:Badawi Karim Badawi]<br />
[[:User:Kroell| Harald Kröll]]<br />
[http://www.iis.ee.ethz.ch/portrait/staff/weberbe.en.html Benjamin Weber]<br />
<br />
<br />
<br />
==Active Projects==<br />
These are the projects that are currently active<br />
<DynamicPageList><br />
category = In progress<br />
category = Telecommunications<br />
</DynamicPageList><br />
---><br />
<br />
<br />
==Available Projects==<br />
We are still looking for students/partners to work on the following projects<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Telecommunications<br />
</DynamicPageList></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Category:Telecommunications&diff=924Category:Telecommunications2015-02-04T09:25:33Z<p>Belfanti: Created page with "==Telecommunications== ==Active Projects== These are the projects that are currently active <DynamicPageList> category = In progress category = Telecommunications </DynamicP..."</p>
<hr />
<div>==Telecommunications==<br />
<br />
<br />
==Active Projects==<br />
These are the projects that are currently active<br />
<DynamicPageList><br />
category = In progress<br />
category = Telecommunications<br />
</DynamicPageList><br />
---><br />
<br />
<br />
==Available Projects==<br />
We are still looking for students/partners to work on the following projects<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = Telecommunications<br />
</DynamicPageList></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Digital_Transmitter_for_Mobile_Communications&diff=923Digital Transmitter for Mobile Communications2015-02-04T09:18:11Z<p>Belfanti: /* Short Description */</p>
<hr />
<div>[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]]<br />
==Short Description==<br />
In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the transceiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. <br />
The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver. <br />
<br />
The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a protocol tester and you will then be able to actually send data over the air.<br />
<br />
This project will give you insight into all parts of a modern 3G standard, such a coding, rate-matching, mapping and the digital frontend.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 20% Theory/MATLAB<br />
: 30% VHDL<br />
: 50% Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Digital_Transmitter_for_Mobile_Communications&diff=922Digital Transmitter for Mobile Communications2015-02-04T09:13:36Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]]<br />
==Short Description==<br />
In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the transceiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. <br />
The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver. <br />
<br />
The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
: Interest in Mobile Communications<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini] <br />
---><br />
===Character===<br />
: 20% Theory/MATLAB<br />
: 30% VHDL<br />
: 50% Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Channel_Estimation_and_Equalization_for_LTE_Advanced&diff=921Channel Estimation and Equalization for LTE Advanced2015-02-04T09:10:59Z<p>Belfanti: /* Short Description */</p>
<hr />
<div>[[File:Channel Estimation and Equalization for LTE Advanced.jpg|thumb|400px]]<br />
==Short Description==<br />
LTE Advanced, the latest 4G mobile communications standard, will provide data rates of up to 3Gbps. It employs OFDM as a highly effective way to deal with frequency selective channels. For optimal performance an accurate channel estimation is crucial to reconstruct the transmitted symbols. Your task will be the development and hardware implementation of a channel estimator and equalizer for LTE Advanced. You will compare existing algorithms in MATLAB and come up with an efficient solution suitable for hardware implementation. <br />
<br />
Depending on your preferences you can the either start working on a novel algorithm in MATLAB or you implement your solution in VHDL, perform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into the most advanced mobile communications standard (LTE Advanced), OFDM, channel estimation algorithms, as well as VLSI design.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 50% VHDL<br />
: 30% Simulation/Theory<br />
: 20% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Channel_Estimation_and_Equalization_for_LTE_Advanced&diff=920Channel Estimation and Equalization for LTE Advanced2015-02-04T09:07:27Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Channel Estimation and Equalization for LTE Advanced.jpg|thumb|400px]]<br />
==Short Description==<br />
LTE Advanced, the latest 4G mobile communications standard, will provide data rates of up to 3Gbps. It employs OFDM as a highly effective way to deal with frequency selective channels. For optimal performance an accurate channel estimation is crucial to reconstruct the transmitted symbols. Your task will be the development and hardware implementation of a channel estimator and equalizer for LTE Advanced. You will start by comparing existing algorithms in MATLAB and come up with an efficient solution suitable for hardware implementation. After the theoretical evaluation has been completed the most promising candidate will then be implemented in VHDL together with an equalizer. Then you will perform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into the most advanced mobile communications standard (LTE Advanced), OFDM, channel estimation algorithms, as well as VLSI design.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 50% VHDL<br />
: 30% Simulation/Theory<br />
: 20% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=Channel_Estimation_and_Equalization_for_LTE_Advanced&diff=919Channel Estimation and Equalization for LTE Advanced2015-02-04T09:07:21Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Channel Estimation and Equalization for LTE Advanced.jpg|thumb|400px]]<br />
==Short Description==<br />
LTE Advanced, the latest 4G mobile communications standard, will provide data rates of up to 3Gbps. It employs OFDM as a highly effective way to deal with frequency selective channels. For optimal performance an accurate channel estimation is crucial to reconstruct the transmitted symbols. Your task will be the development and hardware implementation of a channel estimator and equalizer for LTE Advanced. You will start by comparing existing algorithms in MATLAB and come up with an efficient solution suitable for hardware implementation. After the theoretical evaluation has been completed the most promising candidate will then be implemented in VHDL together with an equalizer. Then you will perform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into the most advanced mobile communications standard (LTE Advanced), OFDM, channel estimation algorithms, as well as VLSI design.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 50% VHDL<br />
: 30% Simulation/Theory<br />
: 20% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top]]<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_High-Throughput_Next_Generation_Turbo_Decoders&diff=918ASIC Implementation of High-Throughput Next Generation Turbo Decoders2015-02-04T09:06:27Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Creating 3D Turbo Codes.jpg|thumb|230px]]<br />
==Short Description==<br />
Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile communications, most modern systems rely on turbo codes because of their outstanding error correction capabilities in conjunction with efficient decoder implementations. For the most recently developed standards with throughput requirements in excess of 1Gbps, providing the necessary throughput has become a real challenge. The IIS has a long history of high-throughput turbo decoders and we have recently had several new ideas on how to improve our architectures even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, you can rely on the expertise from a long line of previous turbo decoders to hopefully develop an outstanding ASIC.<br />
<br />
If you are interested in doing a thesis (semester or master) in the field of error correcting codes, such as turbo codes, just contact [[:User:Belfanti |Sandro Belfanti]] or [[:User:rothc |Christoph Roth]]. There are different projects available, ranging from more theoretical/simulation based projects to the VLSI implementation in form of chip design projects.<br />
<br />
==Previous Turbo Decoders==<br />
[[File:Jetfire2sml overlay white.png|thumb|Turbo decoder ASIC previously fabricated at the IIS]]<br />
All the chips which have been fabricated can be found in the [http://asic.ethz.ch/cg/ IIS chip gallery]. Some examples for turbo decoders designed at the IIS are<br />
<br />
[http://asic.ethz.ch/cg/2010/LaLe.html LaLe: Turbo Decoder for TD-HSPA]<br />
<br />
[http://asic.ethz.ch/cg/2009/LTEturbo.html LTE-Turbo: Turbo Decoder for LTE]<br />
<br />
[http://asic.ethz.ch/cg/2012/Jetfire.html Jetfire: Turbo Decoder for LTE-Advanced]<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Simulation/Theory<br />
: 50% VHDL<br />
: 30% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_High-Throughput_Next_Generation_Turbo_Decoders&diff=916ASIC Implementation of High-Throughput Next Generation Turbo Decoders2015-02-04T09:05:39Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Creating 3D Turbo Codes.jpg|thumb|230px]]<br />
==Short Description==<br />
Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile communications, most modern systems rely on turbo codes because of their outstanding error correction capabilities in conjunction with efficient decoder implementations. For the most recently developed standards with throughput requirements in excess of 1Gbps, providing the necessary throughput has become a real challenge. The IIS has a long history of high-throughput turbo decoders and we have recently had several new ideas on how to improve our architectures even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, you can rely on the expertise from a long line of previous turbo decoders to hopefully develop an outstanding ASIC.<br />
<br />
If you are interested in doing a thesis (semester or master) in the field of error correcting codes, such as turbo codes, just contact [[:User:Belfanti |Sandro Belfanti]] or [[:User:rothc |Christoph Roth]]. There are different projects available, ranging from more theoretical/simulation based projects to the VLSI implementation in form of chip design projects.<br />
<br />
==Previous Turbo Decoders==<br />
[[File:Jetfire2sml overlay white.png|thumb|Turbo decoder ASIC previously fabricated at the IIS]]<br />
All the chips which have been fabricated can be found in the [http://asic.ethz.ch/cg/ IIS chip gallery]. Some examples for turbo decoders designed at the IIS are<br />
<br />
[http://asic.ethz.ch/cg/2010/LaLe.html LaLe: Turbo Decoder for TD-HSPA]<br />
<br />
[http://asic.ethz.ch/cg/2009/LTEturbo.html LTE-Turbo: Turbo Decoder for LTE]<br />
<br />
[http://asic.ethz.ch/cg/2012/Jetfire.html Jetfire: Turbo Decoder for LTE-Advanced]<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti |Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Simulation/Theory<br />
: 50% VHDL<br />
: 30% ASIC Implemenatation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=FPGA-Based_Digital_Frontend_for_3G_Receivers&diff=915FPGA-Based Digital Frontend for 3G Receivers2015-02-04T08:58:35Z<p>Belfanti: /* Links */</p>
<hr />
<div>[[File:Testbed.JPG|thumb|230px]]<br />
==Short Description==<br />
A modern receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received data. <br />
In this project you will work on the very first digital block after the analog part. The received data has to be obtained from the analog frontend, filtered, down-sampled and non-idealities in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).<br />
A complete model of the digital receiver without the DFE has already been developed at the IIS. <br />
In order to work with real data this DFE will be implemented on a FPGA-board, which is connected to an existing analog tranceiver.<br />
Your task will be to implement the DFE on an FPGA and verify the functionality together with the already existing parts.<br />
In the end, the complete chain will be able to receive data which was generated by a protocol tester, transmitted over the air through analog frontend your DFE and the IIS digital baseband receiver.<br />
<br />
This project can either be varied and be done as either a semester or masters thesis.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti]<br />
---><br />
===Character===<br />
: 20% Theory/Simulation<br />
: 50% VHDL<br />
: 30% FPGA Implementation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:FPGA]]<br />
[[Category:System Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Belfanti]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
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TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
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[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Evaluation_Platform_for_Mobile_Communications&diff=657An FPGA-Based Evaluation Platform for Mobile Communications2014-09-22T07:41:42Z<p>Belfanti: </p>
<hr />
<div>==Short Description==<br />
In this project you will implement a simulation environment for mobile communication receivers on an FPGA.<br />
<br />
==Description==<br />
<br />
All parts of a wireless receiver have to be carefully optimized in order to <br />
guarantee optimal performance. This is especially true for the word-widths<br />
of the signals in an implementation. Often, the word-width of every signal<br />
is individually tweaked for an optimal trade-off between performance loss and<br />
area and power consumption. However, this requires many time-consuming <br />
fixed-point simulations to make sure the performance loss is<br />
acceptable. <br />
<br />
In this project you will implement a simulation environment on a<br />
high-end FPGA board to speed up these simulations. The evaluation of<br />
communication algorithms (and decoders in particular) is always similar:<br />
+ Generate random data (bits)<br />
+ Code and modulate<br />
+ [optional: multipath channel]<br />
+ Add noise<br />
+ Receiver/Decoder (Model under Test)<br />
+ Calculate bit error rate (BER)<br />
All of this can be done on an FPGA, therefore greatly accelerating the<br />
simulation speed compared to a MATLAB-based implementation. The<br />
hardware model for the decoder ASIC can easily be transferred to an<br />
FPGA. The task of this project will be do implement the simulation<br />
environment on both the FPGA (random number generation, encoder and<br />
BER calculation) as well as on the PC (communication with the FPGA,<br />
plotting of the results). Several decoders have already been<br />
implemented in previous IIS projects and will be provided to test the setup.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
===Character===<br />
: 65% VHDL / FPGA implementation<br />
: 20% MATLAB implementation<br />
: 15% Testing<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
<!-- [[Category:Available]] ---><br />
[[Category:Semester Thesis]]<br />
[[Category:Available]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=User:Belfanti&diff=656User:Belfanti2014-09-22T07:41:06Z<p>Belfanti: </p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something in with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
* [[Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication|Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication]]<br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar of follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
<br />
== Projects in Progress==<br />
<br />
<br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
[[Category:Supervisors]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Evaluation_Platform_for_Mobile_Communications&diff=655An FPGA-Based Evaluation Platform for Mobile Communications2014-09-22T07:40:28Z<p>Belfanti: </p>
<hr />
<div>==Short Description==<br />
In this project you will implement a simulation environment for mobile communication receivers on an FPGA.<br />
<br />
==Description==<br />
<br />
All parts of a wireless receiver have to be carefully optimized in order to <br />
guarantee optimal performance. This is especially true for the word-widths<br />
of the signals in an implementation. Often, the word-width of every signal<br />
is individually tweaked for an optimal trade-off between performance loss and<br />
area and power consumption. However, this requires many time-consuming <br />
fixed-point simulations to make sure the performance loss is<br />
acceptable. <br />
<br />
In this project you will implement a simulation environment on a<br />
high-end FPGA board to speed up these simulations. The evaluation of<br />
communication algorithms (and decoders in particular) is always similar:<br />
+ Generate random data (bits)<br />
+ Code and modulate<br />
+ [optional: multipath channel]<br />
+ Add noise<br />
+ Receiver/Decoder (Model under Test)<br />
+ Calculate bit error rate (BER)<br />
All of this can be done on an FPGA, therefore greatly accelerating the<br />
simulation speed compared to a MATLAB-based implementation. The<br />
hardware model for the decoder ASIC can easily be transferred to an<br />
FPGA. The task of this project will be do implement the simulation<br />
environment on both the FPGA (random number generation, encoder and<br />
BER calculation) as well as on the PC (communication with the FPGA,<br />
plotting of the results). Several decoders have already been<br />
implemented in previous IIS projects and will be provided to test the setup.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
===Character===<br />
: 65% VHDL / FPGA implementation<br />
: 20% MATLAB implementation<br />
: 15% Testing<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
<!-- [[Category:Available]] ---><br />
[[Category:Semester Thesis]]<br />
<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=User:Belfanti&diff=630User:Belfanti2014-05-21T09:12:27Z<p>Belfanti: </p>
<hr />
<div>==Sandro Belfanti==<br />
Sandro Belfanti was born in Zurich, Switzerland in 1985. He received his M.S. degree in electrical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing<br />
his Ph.D. degree at the integrated systems laboratory (IIS) at ETH Zurich.<br />
<br />
==Interests==<br />
* Digital design<br />
* Wireless communications, mobile communications<br />
* Digital signal processing<br />
* Error correcting codes, turbo codes<br />
* Channel equalization and estimation<br />
<br />
==Available Projects==<br />
<br />
There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis. If you want to do something in with error correction codes or equalizers, <br />
I usually have more ideas for projects than I formulated here, for both more theoretical / simulation-based and implementation projects. If you are interested, just send me an e-mail.<br />
<br />
Group projects (Gruppenarbeiten), are too short to finish any of the projects in this section. However, we do occasionally come across some smaller projects, which we do not post online, so feel free to ask.<br />
<br />
===[[:Category:Digital|Digital Design]]===<br />
<DynamicPageList><br />
category = Available<br />
category = Belfanti<br />
</DynamicPageList><br />
* [[Bandwidth_Extension_with_Carrier_Aggregation_for_Mobile_Gigabit-Communication|Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication]]<br />
<br />
==Completed Projects==<br />
[[File:LazyGonzales.png | thumb | The most recent ASIC from a design project - Lazy Gonzales]]<br />
Projects which have already been completed. Similar of follow-up projects are sometimes possible.<br />
<br />
* Turbo Decoder for LTE-Advanced<br />
* 3D Turbo Codes<br />
* Area-Efficient 3D Turbo Decoder Implementation<br />
* Shuffled Tubo Decoding for LTE-Advanced<br />
* Synchronization for TD-HSPA<br />
* Channel Equalization for Fast Fading Channels in TD-HSPA<br />
<br />
Co-Advisor<br />
* Synchronization & Power Control concepts for 3GPP TD-HSPA<br />
* Co-Channel Interference Cancellation with Receive Diversity<br />
* Digital Frontend for LTE-Advanced<br />
* VLSI Implementation Trade-offs of 3G Turbo Decoders<br />
<br />
== Projects in Progress==<br />
* [[An FPGA-Based Evaluation Platform for Mobile Communications]]<br />
<br />
<br />
==Contact Information==<br />
If you have any questions concerning the projects or are interested in doing something which is not on the list, just write an e-mail.<br />
* '''Office''': ETZ J90<br />
* '''e-mail''': [mailto:belfanti@iis.ee.ethz.ch belfanti@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 260 89<br />
[[Category:Supervisors]]</div>Belfantihttp://iis-projects.ee.ethz.ch/index.php?title=An_FPGA-Based_Evaluation_Platform_for_Mobile_Communications&diff=629An FPGA-Based Evaluation Platform for Mobile Communications2014-05-21T09:10:40Z<p>Belfanti: </p>
<hr />
<div>==Short Description==<br />
In this project you will implement a simulation environment for mobile communication receivers on an FPGA.<br />
<br />
==Description==<br />
<br />
All parts of a wireless receiver have to be carefully optimized in order to <br />
guarantee optimal performance. This is especially true for the word-widths<br />
of the signals in an implementation. Often, the word-width of every signal<br />
is individually tweaked for an optimal trade-off between performance loss and<br />
area and power consumption. However, this requires many time-consuming <br />
fixed-point simulations to make sure the performance loss is<br />
acceptable. <br />
<br />
In this project you will implement a simulation environment on a<br />
high-end FPGA board to speed up these simulations. The evaluation of<br />
communication algorithms (and decoders in particular) is always similar:<br />
+ Generate random data (bits)<br />
+ Code and modulate<br />
+ [optional: multipath channel]<br />
+ Add noise<br />
+ Receiver/Decoder (Model under Test)<br />
+ Calculate bit error rate (BER)<br />
All of this can be done on an FPGA, therefore greatly accelerating the<br />
simulation speed compared to a MATLAB-based implementation. The<br />
hardware model for the decoder ASIC can easily be transferred to an<br />
FPGA. The task of this project will be do implement the simulation<br />
environment on both the FPGA (random number generation, encoder and<br />
BER calculation) as well as on the PC (communication with the FPGA,<br />
plotting of the results). Several decoders have already been<br />
implemented in previous IIS projects and will be provided to test the setup.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Belfanti | Sandro Belfanti]]<br />
<br />
===Prerequisites===<br />
: VLSI I<br />
: MATLAB and VHDL is an advantage<br />
<br />
===Character===<br />
: 65% VHDL / FPGA implementation<br />
: 20% MATLAB implementation<br />
: 15% Testing<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]<br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
<br />
==Detailed Task Description==<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
<br />
[[Category:Digital]]<br />
<!-- [[Category:Available]] ---><br />
[[Category:Semester Thesis]]<br />
[[Category:In progress]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Research]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>Belfanti