http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Gimarti&feedformat=atomiis-projects - User contributions [en]2024-03-28T11:13:05ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9578Integrated Information Processing2023-09-20T14:23:23Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9577Integrated Information Processing2023-09-20T14:23:19Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer_Mitigation_Meets_Machine_Learning&diff=9576Jammer Mitigation Meets Machine Learning2023-09-20T14:23:09Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_magic.png|300px|thumb|Jammer mitigation is not exactly magic, but it sure feels like it. (Image made with Midjourney.)]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers. <br />
<br />
The IIP group has been working on jammer mitigation for a few years now, and has already proposed several novel methods for jammer mitation, such as Joint Jammer Mitigation and Data Detection (JMD) [1] or Jammer Mitigation via Subspace Hiding (MASH) [2]. However, these methods are essentially "classical" signal processing methods: They either pose and solve an optimization problem with first-order methods, or they perform a series of linear transformations based on signal theory. <br />
<br />
The goal of this project would be to carry jammer mitigation to the next level by harvesting the power of machine learning. Machine learning has transformed many fields in recent times, and wireless communications is no exception. A prime example is [https://nvlabs.github.io/sionna/ Sionna], a TensorFlow library that has recently been developed by NVIDIA. Sionna allows the simulation of fully differentiable (and hence trainable) wireless communiation systems. <br />
<br />
In this project, the student would use Sionna to make existing jammer mitigation methods trainable, and to come up with completely new trainable receive architectures. On the flip side, adversarial training cold be utilized to answer such questions as: What is the worst jammer? <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basics understanding of digital communication (such as acquired in the lectures Kommunikationssysteme, Communication and Detection Theory, Wireless Communications, or similar)<br />
: Familiarity with Python and MATLAB<br />
: Prior experience with TensorFlow is advantageous but not required<br />
<br />
===Character===<br />
: 60% Programming<br />
: 40% Algorithm Development<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:In_progress]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9575Integrated Information Processing2023-09-20T14:22:51Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer-Resilient_Synchronization_for_Wireless_Communications&diff=9574Jammer-Resilient Synchronization for Wireless Communications2023-09-20T14:22:38Z<p>Gimarti: </p>
<hr />
<div>[[File:Clock_synchronization.jpg|300px|thumb|Synchronization is a prerequisite for most communication schemes. It is usually a straightforward task, but not if there is an ongoing jamming attack.]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers.<br />
<br />
We have already developed several novel methods for jammer mitigation [1], [2], but they all require successfull synchronization between the transmitter and the receiver to get off the ground. In the presence of a jammer, synchronization is obviously much harder to achieve than usually. So far, there are no methods for jammer-resilient synchronization reported in the open literature. <br />
<br />
The goal of this project would therefore be to develop jammer-resilient methods for synchronization. <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basic knowledge in signal processing and/or digital communications<br />
: Familiarity with MATLAB<br />
<br />
===Character===<br />
: 20% Literature Research<br />
: 40% Algorithm Development<br />
: 40% Implementation and Evaluation<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:In_progress]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9573Integrated Information Processing2023-09-20T14:22:00Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer-Resilient_Synchronization_for_Wireless_Communications&diff=9572Jammer-Resilient Synchronization for Wireless Communications2023-09-20T14:21:41Z<p>Gimarti: </p>
<hr />
<div>[[File:Clock_synchronization.jpg|300px|thumb|Synchronization is a prerequisite for most communication schemes. It is usually a straightforward task, but not if there is an ongoing jamming attack.]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers.<br />
<br />
We have already developed several novel methods for jammer mitigation [1], [2], but they all require successfull synchronization between the transmitter and the receiver to get off the ground. In the presence of a jammer, synchronization is obviously much harder to achieve than usually. So far, there are no methods for jammer-resilient synchronization reported in the open literature. <br />
<br />
The goal of this project would therefore be to develop jammer-resilient methods for synchronization. <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basic knowledge in signal processing and/or digital communications<br />
: Familiarity with MATLAB<br />
<br />
===Character===<br />
: 20% Literature Research<br />
: 40% Algorithm Development<br />
: 40% Implementation and Evaluation<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:Ongoing]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer_Mitigation_Meets_Machine_Learning&diff=9571Jammer Mitigation Meets Machine Learning2023-09-20T14:20:57Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_magic.png|300px|thumb|Jammer mitigation is not exactly magic, but it sure feels like it. (Image made with Midjourney.)]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers. <br />
<br />
The IIP group has been working on jammer mitigation for a few years now, and has already proposed several novel methods for jammer mitation, such as Joint Jammer Mitigation and Data Detection (JMD) [1] or Jammer Mitigation via Subspace Hiding (MASH) [2]. However, these methods are essentially "classical" signal processing methods: They either pose and solve an optimization problem with first-order methods, or they perform a series of linear transformations based on signal theory. <br />
<br />
The goal of this project would be to carry jammer mitigation to the next level by harvesting the power of machine learning. Machine learning has transformed many fields in recent times, and wireless communications is no exception. A prime example is [https://nvlabs.github.io/sionna/ Sionna], a TensorFlow library that has recently been developed by NVIDIA. Sionna allows the simulation of fully differentiable (and hence trainable) wireless communiation systems. <br />
<br />
In this project, the student would use Sionna to make existing jammer mitigation methods trainable, and to come up with completely new trainable receive architectures. On the flip side, adversarial training cold be utilized to answer such questions as: What is the worst jammer? <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basics understanding of digital communication (such as acquired in the lectures Kommunikationssysteme, Communication and Detection Theory, Wireless Communications, or similar)<br />
: Familiarity with Python and MATLAB<br />
: Prior experience with TensorFlow is advantageous but not required<br />
<br />
===Character===<br />
: 60% Programming<br />
: 40% Algorithm Development<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:Ongoing]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=9099Main Page2023-05-10T14:54:40Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 7 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
* [[Integrated Devices, Electronics, And Systems|Integrated Devices, Electronics, And Systems]]<br />
<br />
===[[Integrated Devices, Electronics, And Systems|Integrated Devices, Electronics, And Systems Group (Prof. Wang)]]===<br />
* [[Simulation of 2D artificial cilia metasurface in COMSOL]]<br />
* [[An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications]]<br />
* [[Noise Figure Measurement for Cryogenic System]]<br />
* [[Design of a D-Band Variable Gain Amplifier for 6G Communication]]<br />
* [[Super Resolution Radar/Imaging at mm-Wave frequencies]]<br />
* [[Machine Learning Assisted Direct Synthesis of Passive Networks]]<br />
* [[High resolution, low power Sigma Delta ADC]]<br />
* [[Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Dr. Burger)]]===<br />
* [[Analog IC Design]]<br />
* [[Mixed Signal IC Design]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
<!--* [[High-Performance & V2X Cellular Communications]]---><br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical Circuits, Systems, and Applications]]<br />
** [[Digital Medical Ultrasound Imaging]]<br />
**[[Flexible Electronic Systems and Embedded Epidermal Devices]]<br />
** [[Human Intranet]]<br />
<!-- ** [[Biomedical System on Chips]] --><br />
** [[Wearables for Sports and Fitness Tracking]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available <br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=9098Main Page2023-05-10T14:54:37Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER> <br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 7 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
* [[Integrated Devices, Electronics, And Systems|Integrated Devices, Electronics, And Systems]]<br />
<br />
===[[Integrated Devices, Electronics, And Systems|Integrated Devices, Electronics, And Systems Group (Prof. Wang)]]===<br />
* [[Simulation of 2D artificial cilia metasurface in COMSOL]]<br />
* [[An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications]]<br />
* [[Noise Figure Measurement for Cryogenic System]]<br />
* [[Design of a D-Band Variable Gain Amplifier for 6G Communication]]<br />
* [[Super Resolution Radar/Imaging at mm-Wave frequencies]]<br />
* [[Machine Learning Assisted Direct Synthesis of Passive Networks]]<br />
* [[High resolution, low power Sigma Delta ADC]]<br />
* [[Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Dr. Burger)]]===<br />
* [[Analog IC Design]]<br />
* [[Mixed Signal IC Design]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
<!--* [[High-Performance & V2X Cellular Communications]]---><br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical Circuits, Systems, and Applications]]<br />
** [[Digital Medical Ultrasound Imaging]]<br />
**[[Flexible Electronic Systems and Embedded Epidermal Devices]]<br />
** [[Human Intranet]]<br />
<!-- ** [[Biomedical System on Chips]] --><br />
** [[Wearables for Sports and Fitness Tracking]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available <br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9097Integrated Information Processing2023-05-10T14:54:28Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer-Resilient_Synchronization_for_Wireless_Communications&diff=9096Jammer-Resilient Synchronization for Wireless Communications2023-05-10T14:54:08Z<p>Gimarti: </p>
<hr />
<div>[[File:Clock_synchronization.jpg|300px|thumb|Synchronization is a prerequisite for most communication schemes. It is usually a straightforward task, but not if there is an ongoing jamming attack.]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers.<br />
<br />
We have already developed several novel methods for jammer mitigation [1], [2], but they all require successfull synchronization between the transmitter and the receiver to get off the ground. In the presence of a jammer, synchronization is obviously much harder to achieve than usually. So far, there are no methods for jammer-resilient synchronization reported in the open literature. <br />
<br />
The goal of this project would therefore be to develop jammer-resilient methods for synchronization. <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basic knowledge in signal processing and/or digital communications<br />
: Familiarity with MATLAB<br />
<br />
===Character===<br />
: 20% Literature Research<br />
: 40% Algorithm Development<br />
: 40% Implementation and Evaluation<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer-Resilient_Synchronization_for_Wireless_Communications&diff=9095Jammer-Resilient Synchronization for Wireless Communications2023-05-10T14:53:57Z<p>Gimarti: Created page with "File:Clock_synchronization.jpg|300px|thumb|Synchronization is a prerequisite for most communication schemes. It is usually a straightforward task, but not if there is an ong..."</p>
<hr />
<div>[[File:Clock_synchronization.jpg|300px|thumb|Synchronization is a prerequisite for most communication schemes. It is usually a straightforward task, but not if there is an ongoing jamming attack.]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers.<br />
<br />
We have already developed several novel methods for jammer mitigation [1], [2], but they all require successfull synchronization between the transmitter and the receiver to get off the ground. In the presence of a jammer, synchronization is obviously much harder to achieve than usually. So far, there are no methods for jammer-resilient synchronization reported in the open literature. <br />
<br />
The goal of this project would therefore be to develop jammer-resilient methods for synchronization. <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basic knowledge in signal processing and/or digital communications<br />
: Familiarity MATLAB<br />
<br />
===Character===<br />
: 20% Literature Research<br />
: 40% Algorithm Development<br />
: 40% Implementation and Evaluation<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=File:Clock_synchronization.jpg&diff=9094File:Clock synchronization.jpg2023-05-10T14:50:12Z<p>Gimarti: </p>
<hr />
<div></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9093Integrated Information Processing2023-05-10T14:32:06Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---> <br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Jammer_Mitigation_Meets_Machine_Learning&diff=9092Jammer Mitigation Meets Machine Learning2023-05-10T14:31:45Z<p>Gimarti: Created page with "Jammer mitigation is not exactly magic, but it sure feels like it. (Image made with Midjourney.) ==Short Description== As w..."</p>
<hr />
<div>[[File:jammer_mitigation_magic.png|300px|thumb|Jammer mitigation is not exactly magic, but it sure feels like it. (Image made with Midjourney.)]]<br />
<br />
==Short Description== <br />
<br />
As wireless communication becomes an indispensable pillar of modern infrastructure, jamming attacks turn into a crucial security threat. The widespread adoption of safety-critical technologies such as autonomous driving or industry 4.0 will therefore depend (among many other things) on our ability to mitigate jammers. <br />
<br />
The IIP group has been working on jammer mitigation for a few years now, and has already proposed several novel methods for jammer mitation, such as Joint Jammer Mitigation and Data Detection (JMD) [1] or Jammer Mitigation via Subspace Hiding (MASH) [2]. However, these methods are essentially "classical" signal processing methods: They either pose and solve an optimization problem with first-order methods, or they perform a series of linear transformations based on signal theory. <br />
<br />
The goal of this project would be to carry jammer mitigation to the next level by harvesting the power of machine learning. Machine learning has transformed many fields in recent times, and wireless communications is no exception. A prime example is [https://nvlabs.github.io/sionna/ Sionna], a TensorFlow library that has recently been developed by NVIDIA. Sionna allows the simulation of fully differentiable (and hence trainable) wireless communiation systems. <br />
<br />
In this project, the student would use Sionna to make existing jammer mitigation methods trainable, and to come up with completely new trainable receive architectures. On the flip side, adversarial training cold be utilized to answer such questions as: What is the worst jammer? <br />
<br />
[1] G. Marti and C. Studer, "Joint Jammer Mitigation and Data Detection for Smart, Distributed, and Multi-Antenna Jammers," to be presented at IEEE ICC 2023<br />
<br />
[2] G. Marti and C. Studer, "Universal MIMO Jammer Mitigation via Secret Temporal Subspace Embeddings," arXiv:2305.01260<br />
<br />
===Status: Available===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Basics understanding of digital communication (such as acquired in the lectures Kommunikationssysteme, Communication and Detection Theory, Wireless Communications, or similar)<br />
: Familiarity with Python and MATLAB<br />
: Prior experience with TensorFlow is advantageous but not required<br />
<br />
===Character===<br />
: 60% Programming<br />
: 40% Algorithm Development<br />
<br />
===Professor===<br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<br />
<br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=File:Jammer_mitigation_magic.png&diff=9091File:Jammer mitigation magic.png2023-05-10T14:23:06Z<p>Gimarti: made with midjourney</p>
<hr />
<div>made with midjourney</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9090Integrated Information Processing2023-05-10T11:36:38Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2023===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2023<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9089Integrated Information Processing2023-05-10T11:33:43Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9088Integrated Information Processing2023-05-10T11:33:39Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---> <br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Weak-strong_massive_MIMO_communication_with_low-resolution_ADCs&diff=9087Weak-strong massive MIMO communication with low-resolution ADCs2023-05-10T11:33:34Z<p>Gimarti: </p>
<hr />
<div>[[File:Weak strong.png|500px|thumb|Hybrid architecture for enabling weak-strong communications for massive MIMO basestations equipped with low-resolution data converters.]]<br />
==Short Description==<br />
<br />
Massive multi-antenna (MIMO) technology is a cornerstone of current (5G) and future wireless communication systems that enables the operation of multiple users (MU) within the same time-frequency domain. <br />
However, the implementation of massive MIMO systems creates significant challenges in terms of power consumption, circuit complexity, and cost. To address these challenges, massive MIO basestations will <br />
have to rely on low-resolution analog-to-digital converters (ADCs). However, the use of such low-resolution ADCs creates new difficulties. One of them is the necessity of meticulous power control on the <br />
user side to ensure that the basestation receive signals are equally strong for all users. Otherwise, stronger users would simply drown weaker users in quantization noise. <br />
<br />
The goal of this project is to alleviate the dependency on power control in low-resolution massive MU-MIMO systems by using an analog signal transform prior to data conversion. To this end, we will build<br />
on insights gained in our recent works on low-resolution jammer mitigation [1], [2]. After familiarizing yourself with these works, you will develop a linear transform suited for implementation in analog <br />
that can alleviate the burden of strong users on low-resolution ADCs while allowing the successful detection of all user signals.<br />
<br />
<br />
[1] G. Marti, O. Castañeda, and C. Studer, "Jammer Mitigation via Beam-Slicing for Low-Resolution mmWave Massive MU-MIMO", IEEE Open Journal of Circuits and Systems, Vol. 2, pp. 820-832, Dec. 2021<br />
<br />
[2] G. Marti, O. Castañeda, S. Jacobsson, G. Durisi, T. Goldstein, and C. Studer, "Hybrid Jammer Mitigation for All-Digital mmWave Massive MU-MIMO", 2021 Asilomar Conference on Signals, Systems, and Computers<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: A solid foundation in linear algebra<br />
: Familiarity with the basics of digital or wireless communication<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research<br />
: 40% Algorithm development<br />
: 40% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Completed]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2023]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=9086Novel Methods for Jammer Mitigation2023-05-10T11:32:44Z<p>Gimarti: </p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Completed]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2022]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9085Integrated Information Processing2023-05-10T11:32:04Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=9084Integrated Information Processing2023-05-10T11:32:00Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---> <br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=9083ASIC Implementation of Jammer Mitigation2023-05-10T11:31:48Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms. <br />
<br />
The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology. <br />
<br />
<br />
[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.<br />
<br />
[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.<br />
<br />
[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Completed]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
[[Category:2022]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=9082ASIC Implementation of Jammer Mitigation2023-05-10T11:30:41Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms. <br />
<br />
The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology. <br />
<br />
<br />
[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.<br />
<br />
[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.<br />
<br />
[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Completed]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=7818Integrated Information Processing2022-06-01T09:34:17Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:IIP_overview_nov_2020-v1.png|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Nonlinear Digital Signal Processing]]====<br />
Nonlinearities play a critical role in a large number of signal processing applications, including<br />
the areas of wireless communication, image processing, and machine learning. Unfortunately, analyzing<br />
the fundamental properties of nonlinear systems and estimating signals from nonlinear measurements are<br />
notoriously difficult tasks. The projects in this area focus on analyzing nonlinear systems and developing new algorithms that compensate nonlinear behavior or estimate quantities from nonlinear observation models.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=7817Integrated Information Processing2022-06-01T09:34:12Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---> <br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:IIP_overview_nov_2020-v1.png|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Nonlinear Digital Signal Processing]]====<br />
Nonlinearities play a critical role in a large number of signal processing applications, including<br />
the areas of wireless communication, image processing, and machine learning. Unfortunately, analyzing<br />
the fundamental properties of nonlinear systems and estimating signals from nonlinear measurements are<br />
notoriously difficult tasks. The projects in this area focus on analyzing nonlinear systems and developing new algorithms that compensate nonlinear behavior or estimate quantities from nonlinear observation models.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=7816Main Page2022-06-01T09:34:00Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 6 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
* [[Analog IC Design]]<br />
* [[Biomedical System on Chips]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[High-Performance & V2X Cellular Communications]]<br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available<br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=7815Main Page2022-06-01T09:33:53Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER> <br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 6 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
* [[Analog IC Design]]<br />
* [[Biomedical System on Chips]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[High-Performance & V2X Cellular Communications]]<br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available<br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Weak-strong_massive_MIMO_communication_with_low-resolution_ADCs&diff=7814Weak-strong massive MIMO communication with low-resolution ADCs2022-06-01T09:33:36Z<p>Gimarti: Created page with "Hybrid architecture for enabling weak-strong communications for massive MIMO basestations equipped with low-resolution data converters. ==..."</p>
<hr />
<div>[[File:Weak strong.png|500px|thumb|Hybrid architecture for enabling weak-strong communications for massive MIMO basestations equipped with low-resolution data converters.]]<br />
==Short Description==<br />
<br />
Massive multi-antenna (MIMO) technology is a cornerstone of current (5G) and future wireless communication systems that enables the operation of multiple users (MU) within the same time-frequency domain. <br />
However, the implementation of massive MIMO systems creates significant challenges in terms of power consumption, circuit complexity, and cost. To address these challenges, massive MIO basestations will <br />
have to rely on low-resolution analog-to-digital converters (ADCs). However, the use of such low-resolution ADCs creates new difficulties. One of them is the necessity of meticulous power control on the <br />
user side to ensure that the basestation receive signals are equally strong for all users. Otherwise, stronger users would simply drown weaker users in quantization noise. <br />
<br />
The goal of this project is to alleviate the dependency on power control in low-resolution massive MU-MIMO systems by using an analog signal transform prior to data conversion. To this end, we will build<br />
on insights gained in our recent works on low-resolution jammer mitigation [1], [2]. After familiarizing yourself with these works, you will develop a linear transform suited for implementation in analog <br />
that can alleviate the burden of strong users on low-resolution ADCs while allowing the successful detection of all user signals.<br />
<br />
<br />
[1] G. Marti, O. Castañeda, and C. Studer, "Jammer Mitigation via Beam-Slicing for Low-Resolution mmWave Massive MU-MIMO", IEEE Open Journal of Circuits and Systems, Vol. 2, pp. 820-832, Dec. 2021<br />
<br />
[2] G. Marti, O. Castañeda, S. Jacobsson, G. Durisi, T. Goldstein, and C. Studer, "Hybrid Jammer Mitigation for All-Digital mmWave Massive MU-MIMO", 2021 Asilomar Conference on Signals, Systems, and Computers<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: A solid foundation in linear algebra<br />
: Familiarity with the basics of digital or wireless communication<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research<br />
: 40% Algorithm development<br />
: 40% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=File:Weak_strong.png&diff=7813File:Weak strong.png2022-06-01T09:31:48Z<p>Gimarti: Hybrid architecture for enabling weak-strong communications for massive MIMO basestations equipped with low-resolution data converters.</p>
<hr />
<div>Hybrid architecture for enabling weak-strong communications for massive MIMO basestations equipped with low-resolution data converters.</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=7762Integrated Information Processing2022-04-26T09:13:15Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:IIP_overview_nov_2020-v1.png|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Nonlinear Digital Signal Processing]]====<br />
Nonlinearities play a critical role in a large number of signal processing applications, including<br />
the areas of wireless communication, image processing, and machine learning. Unfortunately, analyzing<br />
the fundamental properties of nonlinear systems and estimating signals from nonlinear measurements are<br />
notoriously difficult tasks. The projects in this area focus on analyzing nonlinear systems and developing new algorithms that compensate nonlinear behavior or estimate quantities from nonlinear observation models.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=7761Integrated Information Processing2022-04-26T09:13:10Z<p>Gimarti: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas: <br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:IIP_overview_nov_2020-v1.png|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Nonlinear Digital Signal Processing]]====<br />
Nonlinearities play a critical role in a large number of signal processing applications, including<br />
the areas of wireless communication, image processing, and machine learning. Unfortunately, analyzing<br />
the fundamental properties of nonlinear systems and estimating signals from nonlinear measurements are<br />
notoriously difficult tasks. The projects in this area focus on analyzing nonlinear systems and developing new algorithms that compensate nonlinear behavior or estimate quantities from nonlinear observation models.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=7760Main Page2022-04-26T09:12:37Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 6 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
* [[Analog IC Design]]<br />
* [[Biomedical System on Chips]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[High-Performance & V2X Cellular Communications]]<br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available<br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=7759Main Page2022-04-26T09:12:29Z<p>Gimarti: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich]. <br />
<br />
==Institute Organization==<br />
The IIS Consists of 6 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
* [[Analog IC Design]]<br />
* [[Biomedical System on Chips]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[High-Performance & V2X Cellular Communications]]<br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available<br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7758ASIC Implementation of Jammer Mitigation2022-04-26T08:25:24Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms. <br />
<br />
The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology. <br />
<br />
<br />
[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.<br />
<br />
[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.<br />
<br />
[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7757ASIC Implementation of Jammer Mitigation2022-04-26T08:24:10Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms. <br />
<br />
The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology. <br />
<br />
[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.<br />
<br />
[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.<br />
<br />
[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7756ASIC Implementation of Jammer Mitigation2022-04-26T08:19:49Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7755ASIC Implementation of Jammer Mitigation2022-04-26T08:17:37Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7754ASIC Implementation of Jammer Mitigation2022-04-26T08:17:23Z<p>Gimarti: </p>
<hr />
<div>[[File:jammer_mitigation_asic.png|400px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=ASIC_Implementation_of_Jammer_Mitigation&diff=7753ASIC Implementation of Jammer Mitigation2022-04-26T08:16:26Z<p>Gimarti: Created page with "A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference. ==Short D..."</p>
<hr />
<div>[[File:jammer_mitigation_asic.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Verilog or VHDL<br />
: VLSI II<br />
: Familiarity with the basics of digital communication is recommended but not strictly required<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 80% VLSI Implementation and Verification<br />
: 20% MATLAB simulation<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=File:Jammer_mitigation_asic.png&diff=7752File:Jammer mitigation asic.png2022-04-26T08:15:27Z<p>Gimarti: A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.</p>
<hr />
<div>A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.</div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=6879Novel Methods for Jammer Mitigation2021-09-02T07:34:57Z<p>Gimarti: </p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=6878Novel Methods for Jammer Mitigation2021-09-01T15:18:08Z<p>Gimarti: </p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=6877Novel Methods for Jammer Mitigation2021-09-01T15:16:30Z<p>Gimarti: </p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). <br />
<br />
Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=6876Novel Methods for Jammer Mitigation2021-09-01T15:14:48Z<p>Gimarti: </p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.<br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Methods_for_Jammer_Mitigation&diff=6875Novel Methods for Jammer Mitigation2021-09-01T15:13:24Z<p>Gimarti: Created page with "A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference. ==Short Description=..."</p>
<hr />
<div>[[File:mimo_jammer.png|400px|thumb|A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.]]<br />
==Short Description==<br />
<br />
Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements). Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data. <br />
<br />
The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.<br />
<br />
===Status: Available ===<br />
: Looking for a Semester/Master student<br />
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]<br />
<br />
===Prerequisites===<br />
: Communication Systems (recommended)<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 20% Literature research <br />
: 30% Theory<br />
: 50% System-level simulation and evaluation<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang] ---><br />
<!--: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=80923 Mathieu Luisier] ---><br />
<!--: [https://ee.ethz.ch/the-department/people-a-z/person-detail.MjUwODc0.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Taekwang Jang] ---><br />
: [https://ee.ethz.ch/the-department/faculty/professors/person-detail.OTY5ODg=.TGlzdC80MTEsMTA1ODA0MjU5.html Christoph Studer]<br />
<!-- : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=79172 Andreas Schenk] ---><br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_5G]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
<br />
[[Category:cat2]]<br />
[[Category:cat3]]<br />
[[Category:cat4]]<br />
[[Category:cat5]]<br />
<br />
<br />
[[Category:Digital]]<br />
SUB CATEGORIES<br />
NEW CATEGORIES<br />
[[Category:Computer Architecture]]<br />
[[Category:Acceleration and Transprecision]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:Event-Driven Computing]]<br />
[[Category:Predictable Execution]]<br />
[[Category:SmartSensors]]<br />
[[Category:Transient Computing]]<br />
[[Category:System on Chips for IoTs]]<br />
[[Category:Energy Efficient Autonomous UAVs]]<br />
[[Category:Biomedical System on Chips]]<br />
[[Category:Digital Medical Ultrasound Imaging]]<br />
[[Category:Cryptography]]<br />
[[Category:Deep Learning Acceleration]]<br />
[[Category:Hyperdimensional Computing]] <br />
<br />
[[Category:Competition]] <br />
[[Category:EmbeddedAI]] <br />
<br />
<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
<br />
[[Category:System Design]]<br />
[[Category:Processor]]<br />
[[Category:Telecommunications]]<br />
[[Category:Modelling]]<br />
[[Category:Software]]<br />
[[Category:Audio]]<br />
<br />
[[Category:Analog]]<br />
[[Category:Nano-TCAD]]<br />
<br />
[[Category:AnalogInt]]<br />
SUB CATEGORIES<br />
[[Category:Telecommunications]]<br />
<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
<br />
TYPE OF WORK<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:Oprecomp]]<br />
[[Category:Antarex]]<br />
[[Category:Hercules]]<br />
[[Category:Icarium]]<br />
[[Category:PULP]]<br />
[[Category:ArmaSuisse]]<br />
[[Category:Mnemosene]]<br />
[[Category:Aloha]]<br />
[[Category:Ampere]]<br />
[[Category:ExaNode]]<br />
[[Category:EPI]]<br />
[[Category:Fractal]]<br />
<br />
<br />
YEAR (IF FINISHED)<br />
[[Category:2010]]<br />
[[Category:2011]]<br />
[[Category:2012]]<br />
[[Category:2013]]<br />
[[Category:2014]]<br />
[[Category:2015]]<br />
[[Category:2016]]<br />
[[Category:2017]]<br />
[[Category:2018]]<br />
[[Category:2019]]<br />
[[Category:2020]]<br />
<br />
<br />
---></div>Gimartihttp://iis-projects.ee.ethz.ch/index.php?title=File:Mimo_jammer.png&diff=6874File:Mimo jammer.png2021-09-01T15:10:22Z<p>Gimarti: A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.</p>
<hr />
<div>A jammer tries to disrupt multiple user equipments from transmitting data to a basestation by injecting interference.</div>Gimarti