http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Guichemerre&feedformat=atomiis-projects - User contributions [en]2024-03-29T07:30:58ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=8587Integrated Information Processing2023-01-25T12:57:39Z<p>Guichemerre: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=8586Integrated Information Processing2023-01-25T12:51:38Z<p>Guichemerre: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Machine-Learning-Based Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Mixed-Signal Circuit Design]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=8585Integrated Information Processing2023-01-25T12:50:22Z<p>Guichemerre: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 1 1 852 740 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 953 1 1802 740 [[Positioning with Wireless Signals]]<br />
rect 1903 1 2751 740 [[Simultaneous Sensing and Communication]]<br />
rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]<br />
rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]<br />
rect 1903 800 2751 1540 [[Real-Time Optimization]]<br />
rect 2853 800 3702 1540 [[Machine-Learning-Based Audio Signal Processing]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_SAR_ADC_for_next_generation_wireless_communication_in_12nm_FinFET&diff=8584High-Speed SAR ADC for next generation wireless communication in 12nm FinFET2023-01-25T12:30:44Z<p>Guichemerre: </p>
<hr />
<div>[[File:idefix.png|400px|thumb|right|Idefix, our first generation high-speed ADC in GlobalFoundries 22nm SOI technology]]<br />
<br />
==Short Description==<br />
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.<br />
<br />
As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.<br />
<br />
A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of SAR ADCs<br />
<br />
===Character===<br />
: 10% Exploring the GF 12LP FinFET technology<br />
: 70% Analog Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_MIXED]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8583High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-25T12:29:47Z<p>Guichemerre: </p>
<hr />
<div>[[File:Garamon_gold.JPG|300px|thumb|right|Garamon, one of the massive-MIMO digital receiver designed by the IIP group]]<br />
<br />
<br />
==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
<br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
<br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==<br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:IIP]]<br />
[[Category:IIP_MIXED]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=8582Integrated Information Processing2023-01-25T12:28:06Z<p>Guichemerre: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Mixed-Signal Circuit Design]]====<br />
All-digital beamforming architectures for massive multi-antenna (MIMO) wireless systems provide best-in-class beamsteering capabilities and simplify many baseband processing tasks. The drawback of such architectures is the need for a large number of radio-frequency (RF) frontends (FEs), which can result in high power consumption and large silicon area. The projects in this area focus on jointly designing and optimizing mixed-signal RF circuits and digital baseband processing implementations to avoid the drawbacks of all-digital beamformers.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Mixed-Signal_Circuit_Design&diff=8581Mixed-Signal Circuit Design2023-01-25T12:26:46Z<p>Guichemerre: Created page with "==Available Projects== <DynamicPageList> suppresserrors = true category = Available category = IIP_MIXED </DynamicPageList>"</p>
<hr />
<div>==Available Projects==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_MIXED<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Integrated_Information_Processing&diff=8580Integrated Information Processing2023-01-25T12:24:03Z<p>Guichemerre: </p>
<hr />
<div><!-- = Integrated Information Processing Group = ---><br />
<br />
The [http://iip.ethz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas:<br />
<br />
__NOTOC__<br />
<imagemap><br />
Image:iip_presentation_jan23.jpg|800px<br />
rect 15 530 630 15 [[Theory, Algorithms, and Hardware for Beyond 5G]]<br />
rect 700 530 1315 15 [[Positioning with Wireless Signals]]<br />
rect 1400 530 2010 15 [[Simultaneous Sensing and Communication]]<br />
rect 2100 530 2720 15 [[All-Digital In-Memory Processing]]<br />
rect 15 1100 630 585 [[Analog-to-Information Conversion for Low-Power Sensing]]<br />
rect 705 1100 1315 585 [[Nonlinear Digital Signal Processing]]<br />
rect 1400 1100 2010 585 [[Real-Time Optimization]]<br />
rect 2100 1100 2720 585 [[Machine-Learning-Based Audio Signal Processing]]<br />
default [[Integrated Information Processing Group]]<br />
desc none<br />
</imagemap><br />
<br />
<br />
====[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]====<br />
<br />
The main focus of the IIP Group is on theory, algorithm design, and hardware implementation of new technologies for beyond fifth-generation (5G) wireless communication systems. The projects in this area focus on emerging communication technologies including massive MIMO, millimeter-wave (mmWave) and terahertz communication, cell-free massive MIMO, intelligent reflective surfaces, ultra low-latency short-packet transmission, and testbed design for massive MIMO prototyping.<br />
<br />
====[[Positioning with Wireless Signals|Positioning with Wireless Signals]]====<br />
<br />
Indoor positioning and outdoor positioning in urban scenarios of mobile phones is a notoriously difficult task. Recently, tools from machine learning have been used to perform positioning from channel-state information (CSI). The projects in this area focus on channel charting, a new technology developed in the IIP group that enables self-supervised positioning from CSI without the users' consent.<br />
<br />
====[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]====<br />
<br />
Modern wireless systems are equipped with large arrays of parallel radio-frequency (RF) chains. Such RF chains are extremely accurate sensors that can be used not only for high-rate data transmission but also for sensing. The projects in the emerging area of simultaneous sensing and communication (SISCO) are on imaging the area next to the antenna array and on classification of user behavior using machine learning techniques.<br />
<br />
====[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]====<br />
<br />
Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. The projects in this area are in designing all-digital and semi-custom PIM accelerators (application-specific integrated circuits) that can be fabricated with conventional CMOS technologies and for emerging applications in machine learning, signal processing, and wireless communication.<br />
<br />
====[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]====<br />
<br />
Always-on sensors that continuously monitor the environment for certain events must operate with energy-efficient classification and detection pipelines. The projects in this area build upon a novel classification pipeline developed in the IIP group called analog-to-feature (A2F) conversion that directly acquires features in the analog domain using non-uniform wavelet sampling (NUWS). Possible applications are real-time sensing and classification of EEG, ECG, RF, and audio signals.<br />
<br />
====[[Nonlinear Digital Signal Processing]]====<br />
Nonlinearities play a critical role in a large number of signal processing applications, including<br />
the areas of wireless communication, image processing, and machine learning. Unfortunately, analyzing<br />
the fundamental properties of nonlinear systems and estimating signals from nonlinear measurements are<br />
notoriously difficult tasks. The projects in this area focus on analyzing nonlinear systems and developing new algorithms that compensate nonlinear behavior or estimate quantities from nonlinear observation models.<br />
<br />
====[[Real-Time Optimization]]====<br />
Numerical optimization finds use in a large number of fields, including wireless communications, machine learning, imaging, physics, operations research, and control. In a growing number of embedded<br />
applications, convex as well as nonconvex optimization problems must be solved in real-time and with stringent latency constraints. The projects in this area focus on the design of novel algorithms that enable real-time numerical optimization at low latency and in a hardware friendly manner.<br />
<br />
====[[Audio Signal Processing]]====<br />
Machine learning and deep neural networks are currently revolutionizing a variety of applications, including the well-established field of digital signal processing. The projects in this area focus on the design of novel algorithms that enable real-time audio signal processing using emerging tools from digital signal processing and machine learning. The ultimate goal is their realization on digital signal processors (DSPs) or hardware accelerators (FPGAs and ASICs).<br />
<br />
=Available Projects=<br />
<br />
===[[Theory, Algorithms, and Hardware for Beyond 5G|Theory, Algorithms, and Hardware for Beyond 5G]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_5G<br />
</DynamicPageList><br />
<br />
===[[Positioning with Wireless Signals|Positioning with Wireless Signals]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_POS<br />
</DynamicPageList><br />
<br />
===[[Simultaneous Sensing and Communication|Simultaneous Sensing and Communication]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_SISCO<br />
</DynamicPageList><br />
<br />
===[[All-Digital In-Memory Processing|All-Digital In-Memory Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_PIM<br />
</DynamicPageList><br />
<br />
===[[Analog-to-Information Conversion for Low-Power Sensing|Analog-to-Information Conversion for Low-Power Sensing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_A2F<br />
</DynamicPageList><br />
<br />
===[[Nonlinear Digital Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_DSP<br />
</DynamicPageList><br />
<br />
===[[Real-Time Optimization]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_OPT<br />
</DynamicPageList><br />
<br />
===[[Audio Signal Processing]]===<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = Available<br />
category = IIP_AUDIO<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
===2022===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2022<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
===2021===<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = IIP<br />
category = 2021<br />
suppresserrors=true<br />
</DynamicPageList><br />
<br />
==Ongoing Projects==<br />
<br />
<DynamicPageList><br />
category = In progress<br />
category = IIP<br />
suppresserrors=true<br />
</DynamicPageList></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=File:Iip_presentation_jan23.jpg&diff=8579File:Iip presentation jan23.jpg2023-01-25T12:21:39Z<p>Guichemerre: </p>
<hr />
<div></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8571High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T12:34:07Z<p>Guichemerre: </p>
<hr />
<div>[[File:Garamon_gold.JPG|300px|thumb|right|Garamon, one of the massive-MIMO digital receiver designed by the IIP group]]<br />
<br />
<br />
==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
<br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
<br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==<br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=8570Main Page2023-01-19T12:32:31Z<p>Guichemerre: </p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
On this page, you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 6 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
* [[Integrated Information Processing| Integrated Information Processing]]<br />
* [[:Category:Physical Characterization|Physical Characterization]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Dr. Burger)]]===<br />
* [[Analog IC Design]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[High-Performance & V2X Cellular Communications]]<br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[High Performance SoCs]]<br />
* [[Energy Efficient SoCs]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous SoCs]]<br />
* [[Event-Driven Computing]]<br />
* [[HW/SW Safety and Security]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Wireless Communication Systems for the IoT]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical Circuits, Systems, and Applications]]<br />
** [[Digital Medical Ultrasound Imaging]]<br />
** [[Human Intranet]]<br />
** [[Biomedical System on Chips]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[IBM Research]]<br />
* [[Huawei Research]]<br />
<br />
===[[Energy Efficient Circuits and IoT Systems Group| Energy Efficient Circuits and IoT Systems Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = EECIS<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Integrated Information Processing|Integrated Information Processing Group (Prof. Studer)]]===<br />
<DynamicPageList><br />
category = IIP<br />
category = Available<br />
</DynamicPageList><br />
<br />
===[[:Category:Physical Characterization|Physical Characterization Group (Dr.Ciappa)]]===<br />
<DynamicPageList><br />
category = Physical Characterization<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8569High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T09:03:33Z<p>Guichemerre: </p>
<hr />
<div>[[File:Garamon_gold.JPG|300px|thumb|right|Garamon, one of the massive-MIMO digital receiver designed by the IIP group]]<br />
<br />
<br />
==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
<br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
<br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8568High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T09:01:39Z<p>Guichemerre: </p>
<hr />
<div>[[File:Garamon_gold.JPG|400px|thumb|right|Garamon, one of the massive-MIMO digital receiver designed by the IIP group]]<br />
<br />
<br />
==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
<br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
<br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=File:Garamon_gold.JPG&diff=8567File:Garamon gold.JPG2023-01-19T08:59:09Z<p>Guichemerre: </p>
<hr />
<div></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8566High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T08:58:40Z<p>Guichemerre: </p>
<hr />
<div>==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
<br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
<br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8565High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T08:58:02Z<p>Guichemerre: </p>
<hr />
<div>==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of DACs<br />
<br />
===Character===<br />
: 10% Familiarizing yourself with TSMC 65nm<br />
: 70% Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_Digital-to-Analog_Converter_(DAC)_for_massive_MIMO_testing_in_65nm_CMOS&diff=8564High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS2023-01-19T08:57:14Z<p>Guichemerre: Created page with "==Short Description== Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communica..."</p>
<hr />
<div>==Short Description==<br />
Massive antenna array (MIMO) technology is widely believe to be the key to enable millimeter waves (mmWave) to be exploited for future wireless communication, hence allowing to use GHz’s of yet unutilized frequency bands. Thanks to this large free spectrum, larger bandwidth can also be allocated per user, which potentially increases data rate. The Integrated Information Processing (IIP) group lead by Prof. Studer is actively working in this field and produces Application Specific Integrated Circuits (ASIC) that can deal with the high-speed digital processing needed for massive MIMO. <br />
The next generation of IC will be a large mixed-signal chips, including an analog front-end as well as critical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing process very challenging. Indeed, the high-speed DACs that would be required to generate such a quantity of high-bandwidth in-phase and quadrature (IQ) signals are not commercially available. <br />
The goal of the project is to design such a high-speed data converter to enable the testing of massive-MIMO hardware. Speed, linearity and reliability will be prioritized at the expense of power consumption to produce a DAC that cannot be the limiting factor of the tested system. During the first part of the project, you will familiarize yourself with the TSMC 65nm technology. You will then design the DAC. After having verified your design, layout will be also done.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
Analog Integrated Circuits (AIC)<br />
Basic knowledge of DACs<br />
<br />
===Character===<br />
10% Familiarizing yourself with TSMC 65nm<br />
70% Design<br />
20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links==</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Bluetooth_Low_Energy_receiver_in_65nm_CMOS&diff=8533Bluetooth Low Energy receiver in 65nm CMOS2023-01-12T10:24:59Z<p>Guichemerre: </p>
<hr />
<div>[[File:Bluetooth_Smart_Logo.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
With the advent of the Internet of Things (IoT), it is expected that the amount of objects capable of Bluetooth Low Energy (BLE) communication will rise exponentially in the upcoming years. Therefore, the design of power efficient BLE transmitter and receiver is crucial to enable them to be embedded in low-power nodes.<br />
<br />
We are looking for students (Semester or Bachelor thesis) to take part in our on-going design of a BLE receiver. The project could either be focused on an analog part of the chain or on the design and implementation of the digital algorithm that compensate for offsets and then decodes. Many blocks are still to be designed (for example an Automatic Gain Control, AGC) so don’t hesitate to contact us so we can discuss about what you want to do and what is still available!<br />
<br />
<br />
===Status: Completed ===<br />
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s)<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC) for an analog project<br />
: VLSI I for a digital project<br />
<br />
===Character===<br />
: 20% Theory<br />
: 40% Algorithm design / Simulation<br />
: 40% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:Completed]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Bluetooth_Low_Energy_receiver_in_65nm_CMOS&diff=8532Bluetooth Low Energy receiver in 65nm CMOS2023-01-12T10:21:29Z<p>Guichemerre: </p>
<hr />
<div>[[File:Bluetooth_Smart_Logo.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
With the advent of the Internet of Things (IoT), it is expected that the amount of objects capable of Bluetooth Low Energy (BLE) communication will rise exponentially in the upcoming years. Therefore, the design of power efficient BLE transmitter and receiver is crucial to enable them to be embedded in low-power nodes.<br />
<br />
We are looking for students (Semester or Bachelor thesis) to take part in our on-going design of a BLE receiver. The project could either be focused on an analog part of the chain or on the design and implementation of the digital algorithm that compensate for offsets and then decodes. Many blocks are still to be designed (for example an Automatic Gain Control, AGC) so don’t hesitate to contact us so we can discuss about what you want to do and what is still available!<br />
<br />
<br />
===Status: Completed ===<br />
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s)<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC) for an analog project<br />
: VLSI I for a digital project<br />
<br />
===Character===<br />
: 20% Theory<br />
: 40% Algorithm design / Simulation<br />
: 40% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:Completed]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_SAR_ADC_for_next_generation_wireless_communication_in_12nm_FinFET&diff=8531High-Speed SAR ADC for next generation wireless communication in 12nm FinFET2023-01-12T09:27:27Z<p>Guichemerre: </p>
<hr />
<div>[[File:idefix.png|400px|thumb|right|Idefix, our first generation high-speed ADC in GlobalFoundries 22nm SOI technology]]<br />
<br />
==Short Description==<br />
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.<br />
<br />
As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.<br />
<br />
A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of SAR ADCs<br />
<br />
===Character===<br />
: 10% Exploring the GF 12LP FinFET technology<br />
: 70% Analog Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_SAR_ADC_for_next_generation_wireless_communication_in_12nm_FinFET&diff=8530High-Speed SAR ADC for next generation wireless communication in 12nm FinFET2023-01-12T09:20:43Z<p>Guichemerre: </p>
<hr />
<div>[[File:idefix.png|400px|thumb|right|Idefix, our first generation high-speed ADC in GlobalFoundries 22nm SOI technology]]<br />
<br />
==Short Description==<br />
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.<br />
<br />
As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.<br />
<br />
A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of SAR ADCs<br />
<br />
===Character===<br />
: 10% Exploring the GF 12LP FinFET technology<br />
: 70% Analog Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=File:Idefix.png&diff=8529File:Idefix.png2023-01-12T09:18:25Z<p>Guichemerre: Picture of packaged Idefix chip</p>
<hr />
<div>Picture of packaged Idefix chip</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_SAR_ADC_for_next_generation_wireless_communication_in_12nm_FinFET&diff=8528High-Speed SAR ADC for next generation wireless communication in 12nm FinFET2023-01-12T09:15:50Z<p>Guichemerre: </p>
<hr />
<div>==Short Description==<br />
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.<br />
<br />
As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.<br />
<br />
A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of SAR ADCs<br />
<br />
===Character===<br />
: 10% Exploring the GF 12LP FinFET technology<br />
: 70% Analog Design<br />
: 20% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=High-Speed_SAR_ADC_for_next_generation_wireless_communication_in_12nm_FinFET&diff=8527High-Speed SAR ADC for next generation wireless communication in 12nm FinFET2023-01-12T09:14:54Z<p>Guichemerre: Created page with "==Short Description== Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as the..."</p>
<hr />
<div>==Short Description==<br />
Due to the very crowded spectrum at lower frequencies, millimeter waves (mmWave) are to be used for the next generations of wireless communication as they offer wide bands of unused spectrum. However, increasing frequency also means that path loss will become problematic. To overcome this issue, massive multi-antenna (MIMO) technology is widely believe to be the key: a matrix of antenna allows to aim the power in a precise direction, hence concentrating the transmitted power in the direction of the receiver.<br />
<br />
As GHz’s of bandwidth are available at higher carrier frequencies, 5G and beyond 5G technologies are expected to enable higher data-rates than previous generation communication. This leads to high-speed requirement for the Analog-to-Digital Converter (ADC) which needs to digitize in the order of 1GS/s. Thanks to high number of independent front-ends, the resolution of the ADCs doesn’t need to be very high, in the order of 8-10b. However, as each antenna of the MIMO array leads to 2 ADCs, converters need to have a low power consumption, to be of low area, and not to rely on any other bulky blocks that cannot be shared.<br />
<br />
A first generation of such an ADC has been designed in GlobalFoundries (GF) 22fdx technology. For digital circuits, the advantage of scaling to a smaller node is clear, but this is not always the case for analog blocks. Hence, the work of the project will be to explore the new 12nm FinFET technology 12LP from GlobalFoundries by porting the existing 22nm ADC. Purely analog parts will be redesigned fully and exploration will be done about the speed and driving strength of the logic components of the circuits. If time allows it, some layout will also be done for the most sensitive parts of the ADC.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
: Basic knowledge of SAR ADCs<br />
<br />
===Character===<br />
: 10% Exploring the GF 12LP FinFET technology<br />
: 70% Analog Design<br />
: 20% Layout<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Bluetooth_Low_Energy_receiver_in_65nm_CMOS&diff=8526Bluetooth Low Energy receiver in 65nm CMOS2023-01-12T09:00:59Z<p>Guichemerre: </p>
<hr />
<div>[[File:Bluetooth_Smart_Logo.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
With the advent of the Internet of Things (IoT), it is expected that the amount of objects capable of Bluetooth Low Energy (BLE) communication will rise exponentially in the upcoming years. Therefore, the design of power efficient BLE transmitter and receiver is crucial to enable them to be embedded in low-power nodes.<br />
<br />
We are looking for students (Semester or Bachelor thesis) to take part in our on-going design of a BLE receiver. The project could either be focused on an analog part of the chain or on the design and implementation of the digital algorithm that compensate for offsets and then decodes. Many blocks are still to be designed (for example an Automatic Gain Control, AGC) so don’t hesitate to contact us so we can discuss about what you want to do and what is still available!<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s)<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC) for an analog project<br />
: VLSI I for a digital project<br />
<br />
===Character===<br />
: 20% Theory<br />
: 40% Algorithm design / Simulation<br />
: 40% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
'''[[Category:Available]]'''<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Analog_building_blocks_for_mmWave_manipulation&diff=6904Analog building blocks for mmWave manipulation2021-09-15T13:44:10Z<p>Guichemerre: Created page with "File:VCO2.png|400px|thumb|right|M. W. Mansha and M. M. Hella, "A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI," in IEEE Journal..."</p>
<hr />
<div>[[File:VCO2.png|400px|thumb|right|M. W. Mansha and M. M. Hella, "A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI," in IEEE Journal of Solid-State Circuits, May 2021]]<br />
<br />
==Short Description==<br />
While the fifth generation (5G) of wireless communication systems is being commercialized, research is currently being carried out on the next generation of wireless communication systems. To achieve higher data rate and due to spectrum congestion, the sixth generation (6G) is expected to operate at higher carrier frequencies, up to more than a 100GHz. For analog designers, this leads to several challenges, one of them being the generation of such frequencies with a jitter in the range of a few tens of femtoseconds while staying power efficient.<br />
<br />
After having designed an oscillator operating at such frequencies, all the building blocks to manipulate mmWave clocks still need to be designed such that they do not add jitter while remaining power efficient. This project will explore circuits such as dividers, multipliers as well as clock distribution techniques at very-high frequencies in the Globalfoundries 22nm technology node.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor Thesis, Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
<br />
===Character===<br />
: 20% Theory<br />
: 80% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=5G_Cellular_RF_Front-end_Design_in_22nm_CMOS_Technology&diff=69035G Cellular RF Front-end Design in 22nm CMOS Technology2021-09-15T13:36:17Z<p>Guichemerre: </p>
<hr />
<div>[[File:LTE_FE_over.png|thumb]]<br />
==Short Description==<br />
In a transceiver IC, the analog front-end is the first circuit that processes the received<br />
signal from the antenna. In modern transceiver ICs (e.g. for LTE application) the front-end<br />
amplifies the signal prior to a direct downconversion to baseband. Both the amplification<br />
and frequency conversion stage have to show a very low noise figure and have to be free<br />
of harmonic distortion.<br />
As more and more digital functions are integrated on the transceiver IC, ultra-scaled digital<br />
CMOS starts offering big advantages in terms of area and power consumption. Those<br />
technologies pose new challenges and offer new opportunities to the analog front-end<br />
design.<br />
In this work the analog front-end for the up-coming 5G standards will be implemented in<br />
a 22nm CMOS technology. Different topologies for the low-noise-amplifier (LNA)<br />
and the mixer (frequency translation circuit) shall be analyzed and compared. The most<br />
promising will be implemented and verifed in the mentioned IC technology.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits<br />
: Communication Electronics (''recommended'')<br />
===Character===<br />
: 30% Theory<br />
: 60% ASIC Design<br />
: 10% Layout<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] <br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
<br />
[[#top|↑ top]]<br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Analog IC Design]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=A_mmWave_Voltage-Controlled-Oscillator_(VCO)_for_beyond_5G_applications&diff=6902A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications2021-09-15T13:31:43Z<p>Guichemerre: </p>
<hr />
<div>[[File:VCO2.png|400px|thumb|right|M. W. Mansha and M. M. Hella, "A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI," in IEEE Journal of Solid-State Circuits, May 2021]]<br />
<br />
==Short Description==<br />
While the fifth generation (5G) of wireless communication systems is being commercialized, research is currently being carried out on the next generation of wireless communication systems. To achieve higher data rate and due to spectrum congestion, the sixth generation (6G) is expected to operate at higher carrier frequencies, up to more than a 100GHz. For analog designers, this leads to several challenges, one of them being the generation of such frequencies with a jitter in the range of a few tens of femtoseconds while staying power efficient.<br />
<br />
One of the most critical building blocks to generate a high-quality high-frequency clock is the Voltage-Controlled-Oscillator (VCO) that needs to produce very high frequencies while being low-power, showing tuning capabilities and exhibiting low noise. In this project, we will explore the design variable of such a VCO in the modern GlobalFoundries 22nm technology node to later implement a mmWave frequency synthesizer competing with the state-of-the-art.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor Thesis, Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
<br />
===Character===<br />
: 20% Theory<br />
: 80% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=A_mmWave_Voltage-Controlled-Oscillator_(VCO)_for_beyond_5G_applications&diff=6901A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications2021-09-15T13:28:50Z<p>Guichemerre: </p>
<hr />
<div>[[File:VCO2.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
While the fifth generation (5G) of wireless communication systems is being commercialized, research is currently being carried out on the next generation of wireless communication systems. To achieve higher data rate and due to spectrum congestion, the sixth generation (6G) is expected to operate at higher carrier frequencies, up to more than a 100GHz. For analog designers, this leads to several challenges, one of them being the generation of such frequencies with a jitter in the range of a few tens of femtoseconds while staying power efficient.<br />
<br />
One of the most critical building blocks to generate a high-quality high-frequency clock is the Voltage-Controlled-Oscillator (VCO) that needs to produce very high frequencies while being low-power, showing tuning capabilities and exhibiting low noise. In this project, we will explore the design variable of such a VCO in the modern GlobalFoundries 22nm technology node to later implement a mmWave frequency synthesizer competing with the state-of-the-art.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor Thesis, Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
<br />
===Character===<br />
: 20% Theory<br />
: 80% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=File:VCO2.png&diff=6900File:VCO2.png2021-09-15T13:27:34Z<p>Guichemerre: </p>
<hr />
<div>From M. W. Mansha and M. M. Hella, "A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI," in IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1514-1526, May 2021, doi: 10.1109/JSSC.2021.3066121.</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=File:VCO2.png&diff=6899File:VCO2.png2021-09-15T13:26:06Z<p>Guichemerre: </p>
<hr />
<div></div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=A_mmWave_Voltage-Controlled-Oscillator_(VCO)_for_beyond_5G_applications&diff=6898A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications2021-09-15T12:45:33Z<p>Guichemerre: Created page with "right ==Short Description== While the fifth generation (5G) of wireless communication systems is being commercialized, research..."</p>
<hr />
<div>[[File:Bluetooth_Smart_Logo.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
While the fifth generation (5G) of wireless communication systems is being commercialized, research is currently being carried out on the next generation of wireless communication systems. To achieve higher data rate and due to spectrum congestion, the sixth generation (6G) is expected to operate at higher carrier frequencies, up to more than a 100GHz. For analog designers, this leads to several challenges, one of them being the generation of such frequencies with a jitter in the range of a few tens of femtoseconds while staying power efficient.<br />
<br />
One of the most critical building blocks to generate a high-quality high-frequency clock is the Voltage-Controlled-Oscillator (VCO) that needs to produce very high frequencies while being low-power, showing tuning capabilities and exhibiting low noise. In this project, we will explore the design variable of such a VCO in the modern GlobalFoundries 22nm technology node to later implement a mmWave frequency synthesizer competing with the state-of-the-art.<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor Thesis, Semester project or Master Thesis<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC)<br />
<br />
===Character===<br />
: 20% Theory<br />
: 80% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Available]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerrehttp://iis-projects.ee.ethz.ch/index.php?title=Bluetooth_Low_Energy_receiver_in_65nm_CMOS&diff=6897Bluetooth Low Energy receiver in 65nm CMOS2021-09-15T07:22:04Z<p>Guichemerre: </p>
<hr />
<div>[[File:Bluetooth_Smart_Logo.png|400px|thumb|right]]<br />
<br />
==Short Description==<br />
With the advent of the Internet of Things (IoT), it is expected that the amount of objects capable of Bluetooth Low Energy (BLE) communication will rise exponentially in the upcoming years. Therefore, the design of power efficient BLE transmitter and receiver is crucial to enable them to be embedded in low-power nodes.<br />
<br />
We are looking for students (Semester or Bachelor thesis) to take part in our on-going design of a BLE receiver. The project could either be focused on an analog part of the chain or on the design and implementation of the digital algorithm that compensate for offsets and then decodes. Many blocks are still to be designed (for example an Automatic Gain Control, AGC) so don’t hesitate to contact us so we can discuss about what you want to do and what is still available!<br />
<br />
<br />
===Status: Available ===<br />
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s)<br />
: Contact: [mailto:jeremyg@iis.ee.ethz.ch Jérémy Guichemerre], [[:User:Burger | Thomas Burger]]<br />
<br />
===Prerequisites===<br />
: Analog Integrated Circuits (AIC) for an analog project<br />
: VLSI I for a digital project<br />
<br />
===Character===<br />
: 20% Theory<br />
: 40% Algorithm design / Simulation<br />
: 40% Implementation<br />
<br />
<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Analog]]<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Burger]]<br />
[[Category:Analog IC Design]]<br />
[[Category:Telecommunications]]<br />
[[#top|↑ top]]</div>Guichemerre