http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Liaoj&feedformat=atomiis-projects - User contributions [en]2024-03-28T10:19:38ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9646Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-10-11T12:53:32Z<p>Liaoj: </p>
<hr />
<div>[[File:optimal_routing_for_ACiM.png|thumb|1200px]]<br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Completed===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Completed]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9645Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-10-11T12:53:18Z<p>Liaoj: /* Status: Available */</p>
<hr />
<div>[[File:optimal_routing_for_ACiM.png|thumb|1200px]]<br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Completed===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9519Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-08-28T08:31:41Z<p>Liaoj: Liaoj moved page Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture to Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)</p>
<hr />
<div>[[File:optimal_routing_for_ACiM.png|thumb|1200px]]<br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture&diff=9520Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture2023-08-28T08:31:41Z<p>Liaoj: Liaoj moved page Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture to Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)</p>
<hr />
<div>#REDIRECT [[Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9475Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-07-29T10:15:41Z<p>Liaoj: </p>
<hr />
<div>[[File:optimal_routing_for_ACiM.png|thumb|1200px]]<br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9474Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-07-29T10:15:21Z<p>Liaoj: </p>
<hr />
<div>[[File:optimal_routing_for_ACiM.png|thumb|600px]]<br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Optimal_routing_for_ACiM.png&diff=9473File:Optimal routing for ACiM.png2023-07-29T10:14:19Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Optimal_routing_for_2D_Mesh-based_Analog_Compute-In-Memory_Accelerator_Architecture_(IBM-Zurich)&diff=9472Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)2023-07-29T10:13:58Z<p>Liaoj: Created page with " === Description === The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performin..."</p>
<hr />
<div><br />
=== Description ===<br />
The explosive application of deep neural networks to every conceivable domain has led to a consequent interest in acceleration architectures for performing efficient inference of very large networks. While GPUs remain the leading device of choice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed.<br />
In this regard, IBM has designed and demonstrated a 2D mesh-based Analog Compute-In-Memory accelerator for DNN inference, pictured in Figure 1. The accelerator consists of a mesh of nodes, containing a mix of analog-compute tiles that perform efficient Vector-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and with better power efficiency in comparison to SotA works.<br />
One challenge of such mesh-based architectures is that of routing, namely, how are network layers and operations mapped onto the mesh in order to reduce latencies and avoid mesh contention. Such challenges are analogous to those found in fields such as digital circuit and FPGA synthesis, where such algorithms have been studies for decades and a wide variety of open-source libraries are already available.<br />
<br />
In this project, the student will:<br />
1. Study prior art on routing techniques<br />
2. Familiarize themselves with the existing mesh-based architecture<br />
3. Propose and test applicable routing strategies and/or develop new routing strategies.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Dr. William Simon: <[mailto:william.simon1@ibm.com william.simon1@ibm.com]><br />
<br />
===Prerequisites===<br />
* Outstanding programming skills (C/C++ and/or Python)<br />
* Independent learning/working abilities<br />
* Interest in FPGAs and/or digital synthesis flows (note that work will not be with FPGAs or digital synthesis, but applying applicable routing algorithms to mesh-based architectures)<br />
* Strong work ethic<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design<br />
<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
===Working Location===<br />
The work will take place at the IBM Rüschlikon campus<br />
<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2023]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Hardware/software_codesign_neural_decoding_algorithm_for_%E2%80%9Cneural_dust%E2%80%9D&diff=8468Hardware/software codesign neural decoding algorithm for “neural dust”2023-01-09T14:16:49Z<p>Liaoj: /* Reference */</p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Non-invasive BMIs, mostly based on EEG signals, do not require surgery to implant sensing nodes in the brain. However, they strongly suffer from low spatial resolution and low signal-to-noise ratio, making them often not accurate. Implantable BMIs, on the other hand, offer high resolution and high signal quality, making them necessary for applications where decoding accuracy is crucial.<br />
<br />
Minimizing the damage to the brain is one of the primary goals of implantable BMI systems. Most of the existing systems are bulky and wired for communication and power transfer. Wireless, miniaturized, and implantable BMI systems (sometimes called “neural recording dust”) hold the promise of restoring motor function while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area.<br />
<br />
Researchers have developed mm-scale neural probe [1][2] and efficient algorithms [3][4] to tackle the problem. Our goal is to hardware/software codesign novel deep learning algorithm for neural decoding based on the spiking band power (SBP) information from the mm-scale neural probe.<br />
<br />
In this project, the student will:<br />
1. Study prior art<br />
2. Get familiar with the dataset and the system<br />
3. Explore ML algorithms (CNNs, RNNs, SNNs, …)<br />
4. H/S codesign efficient algorithms<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Liao et al., "An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface," 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, pp. 134-137, doi: 10.1109/AICAS54282.2022.9869846.<br />
<br />
[2] M. S. Willsey et al., “Real-time brain-machine interface in non-human primates achieves high-velocity prosthetic finger movements using a shallow feedforward neural network decoder,” Nat Commun, vol. 13, no. 1, Art. no. 1, Nov. 2022, doi: 10.1038/s41467-022-34452-w.<br />
<br />
[3] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[4] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[5] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[6] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Spiking_Neural_Network_for_Motor_Function_Decoding_Based_on_Neural_Dust&diff=8467Spiking Neural Network for Motor Function Decoding Based on Neural Dust2023-01-09T14:15:57Z<p>Liaoj: /* Reference */</p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Researchers have developed mm-scale implantable neural probe [1][2] aiming to restore motor function while reducing the damage caused by the implantation. Such systems pose stringent constraints on the power consumption, area, and latency.<br />
<br />
Spiking neural network (SNN), an emerging brain-inspired algorithm, takes advantage of asynchronous information and computation to achieve low latency and low power consumption. Unlike images or sounds acquired by conventional sensors, the neural signals are naturally asynchronous and encode information in timing and firing rate, which is perfectly compatible with SNN’s requirement for input data. This makes SNN a good candidate for neural decoding, and the nature of neural signals may release more potential of SNN.<br />
<br />
In particular, reservoir-based Liquid State Machine (LSM) [5] is a recurrent computational model which is a more adequate emulation of the biological cortical networks compared to layer-based SNNs. It maps the input spike trains to the output spike trains by means of the so-called Liquid or reservoir, which consists of a recurrent neural network formed by many computational nodes. Kasabov [6] proposed a reservoir-based SNN, named NeuCube, to learn and understand the spatio-temporal features of the brain activities and has been demonstrated to be competitive to layer-based approaches. A very recent work [7] used NeuCube to perform the regression problem of Grasp-and-Lift dataset achieving very promising results.<br />
<br />
In this project, the student will<br />
<br />
1. Study prior art, including and not limited to LSM, SNN<br />
<br />
2. Get familiar with the dataset, the system, and the deep learning framework<br />
<br />
3. Explore and develop SNN to offline decode finger movement<br />
A more detailed project description will be provided tailored to the type of the project (master or semester).<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Liao et al., "An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface," 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, pp. 134-137, doi: 10.1109/AICAS54282.2022.9869846.<br />
<br />
[2] M. S. Willsey et al., “Real-time brain-machine interface in non-human primates achieves high-velocity prosthetic finger movements using a shallow feedforward neural network decoder,” Nat Commun, vol. 13, no. 1, Art. no. 1, Nov. 2022, doi: 10.1038/s41467-022-34452-w.<br />
<br />
[3] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[4] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[5] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[6] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[7] W. Maass, et al., “Real-time computing without stable states: A new framework for neural computation based on perturbations”. In Neural Computation 14, 2002, pp. 2531–2560. <br />
<br />
[8] N. K. Kasabov, "NeuCube: A spiking neural network architecture for mapping, learning and understanding of spatio-temporal brain data." Neural Networks 52, 2014, pp. 62-76.<br />
<br />
[9] Kumarasinghe, et al., D. Brain-inspired spiking neural networks for decoding and understanding muscle activity and kinematics from electroencephalography signals during hand movements. Sci Rep 11, 2486 (2021). https://doi.org/10.1038/s41598-021-81805-4<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Precise_Ultra-low-power_Timer&diff=8459Precise Ultra-low-power Timer2022-12-16T16:04:32Z<p>Liaoj: </p>
<hr />
<div>[[File:LEDonTimer.PNG|thumb|300px]]<br />
[[File:timer_ext_ctrl.PNG|thumb|300px]]<br />
[[File:timer_testboard.PNG|thumb|300px]]<br />
=== Introduction ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operate on the sensor node should be insensitive to temperature variation. Especially for on-chip timers, they have to have high frequency accuracies, meaning that they need to be insensitive to PVT variations and they have to have long-term frequency stability. <br />
<br />
<br />
=== Project Description ===<br />
* Develop a control loop to compensate temperature variation of the on-chip timer.<br />
<br />
===Status: Available===<br />
: Looking for Semester and Master Project Students<br />
: Supervision: [[:User:Liaoj | Jiawei Liao]], Giorgio Cristiano, Hesam Omdeh Ghiasi, Liza Zaper<br />
<br />
===Prerequisites===<br />
* VLSI I<br />
* Solid state device physics will be a plus<br />
<br />
===Professor===<br />
: [https://iis.ee.ethz.ch/people/person-detail.tjang.html Prof. Taekwang Jang] <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Completed]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:FPGA]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=8458Novel Metastability Mitigation Technique2022-12-16T16:03:03Z<p>Liaoj: </p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: In progress===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Completed]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Analog_Compute-in-Memory_Accelerator_Interface_and_Integration&diff=8457Analog Compute-in-Memory Accelerator Interface and Integration2022-12-16T16:02:16Z<p>Liaoj: </p>
<hr />
<div>[[File:FeFET_ACiM.png|thumb|400px]]<br />
=== Description ===<br />
The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the substantial energy and latency needs of off-chip memories. To tackle this issue, researchers have started investigating on structures base on non-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm.<br />
<br />
One of these most novel and promising devices are the ferroelectric FETs (FeFETs), which exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].<br />
<br />
The target for this project is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system. <br />
In this project the student will:<br />
1. Work in close contact with industry partners for the development of a FeFET IMC crossbar (XBAR) array<br />
2. Design interface for ACiM accelerator<br />
3. Integrate the accelerator with MCU<br />
4. Verify functionality of the system<br />
<br />
===Status: In Progress===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* Worked with at least one RTL language in the past (SystemVerilog or Verilog)<br />
* Prior knowledge of hardware design and computer architecture <br />
* VLSI I<br />
* Knowledge of analog circuit is a plus (e.g. AIC)<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Architecture Design <br />
* 30% RTL implementation<br />
* 30% Verification<br />
<br />
===Professor===<br />
[mailto:tjang@ethz.ch Prof. Taekwang Jang]<br />
<br />
=== Reference===<br />
[1] T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750.<br />
<br />
<br />
[2] T. Soliman et al., "Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 29.2.1-29.2.4, doi: 10.1109/IEDM13553.2020.9372124.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
<br />
[[Category:Completed]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_MEMs_Sensor_Interface&diff=7726Design of MEMs Sensor Interface2022-03-10T13:22:01Z<p>Liaoj: </p>
<hr />
<div><br />
=== Description ===<br />
Microelectromechanical systems (MEMs) have been widely used as sensors in different applications such as acoustic sensors. In this domain, MEMs capacitance attracted broad attention due to its high dynamic range and sensitivity relative to the other transducers like electromagnetic or piezoresistive microphone. Optical microphones can play an attractive role as a sensor too, due to its not susceptibility to electrical noise and electromagnetic interferences (then leads to higher dynamic range), but with much higher cost. <br />
<br />
Most of the capacitive MEMs microphone deployed a charge amplifier, as an interface ASIC, after the transducer to maintain the charge. This pre-amplifier needs to be low noise, low power, high input impedance and have good linearity in a sense that it does not create any other harmonics except the main acoustic signal in the input. Thus, the designer needs significant consideration to deal with the aforementioned parameters to adjust them in a coordinated range. <br />
<br />
During this project, students will learn the key trade-offs challenging the engineers in designing sensor interface, deal with MEMs microphone as the main sensor for acoustic wave, design low noise amplifiers and variable gain amplifiers. <br />
<br />
===Status: Available===<br />
:Looking for master students<br />
:Supervisor: Hesam Omdeh Ghiasi <[mailto:hghiasi@ethz.ch hghiasi@iis.ee.ethz.ch]><br />
===Prerequisites===<br />
* Analog Integrated Circuit Design<br />
<br />
===Character===<br />
* 10% Literature review<br />
* 30% Theory<br />
* 60% Circuit Design<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] Jeong, S., Chen, Y., Jang, T., Tsai, J. M. L., Blaauw, D., Kim, H. S., & Sylvester, D. (2018). Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes. IEEE Journal of Solid-State Circuits, 53(1), 261–274. https://doi.org/10.1109/JSSC.2017.2728787<br />
<br />
[2] Oh, S., Cho, M., Member, S., Shi, Z., Lim, J., Member, S., Kim, Y., Jeong, S., Member, S., Chen, Y., Rothe, R., Member, S., Blaauw, D., Kim, H., & Sylvester, D. (2019). An Acoustic Signal Processing Chip With 142-nW Voice Activity Detection Using Mixer-Based Sequential Frequency Scanning and. 54(11), 3005–3016.<br />
<br />
[3] Shen, L., Member, S., Lu, N., Sun, N., & Member, S. (2018). A 1-V 0 . 25- μ W Inverter Stacking Amplifier With 1 . 07 Noise Efficiency Factor. 53(3), 896–905.<br />
<br />
[4] Zawawi, S. A., Hamzah, A. A., & Majlis, B. Y. (2020). A Review of MEMS Capacitive Microphones. 1–26.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:In progress]]<br />
[[Category:2021]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=7660Novel Metastability Mitigation Technique2022-02-21T09:11:21Z<p>Liaoj: </p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: In progress===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:In progress]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=7659Novel Metastability Mitigation Technique2022-02-21T09:10:08Z<p>Liaoj: </p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: Active===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Active]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Energy_Efficient_Circuits_and_IoT_Systems_Group&diff=7658Energy Efficient Circuits and IoT Systems Group2022-02-21T09:06:57Z<p>Liaoj: /* Active Projects */</p>
<hr />
<div>__NOTOC__<br />
<imagemap><br />
Image:Project_outline.jpg|900px<br />
rect 0 1101 1125 0 [[Design of key building blocks for miniaturized sensor systems]]<br />
rect 1140 1101 2255 0 [[Energy Efficient Circuits for Wireless Neural Recording]]<br />
rect 2278 1101 3418 0 [[Application Specific Frequency Synthesizers (Analog/Digital PLLs)]]<br />
default [[Energy Efficient Circuits and IoT Systems Group]]<br />
desc none<br />
</imagemap><br />
<br />
__NOTOC__<br />
==Available Projects==<br />
<br />
<br />
<DynamicPageList><br />
category = Available<br />
category = EECIS<br />
</DynamicPageList><br />
<br />
==Active Projects==<br />
<DynamicPageList><br />
suppresserrors = true<br />
category = In progress<br />
category = EECIS<br />
</DynamicPageList><br />
<br />
==Completed Projects==<br />
<br />
<DynamicPageList><br />
category = Completed<br />
category = EECIS<br />
</DynamicPageList></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=7657Low-power Temperature-insensitive Timer2022-02-21T09:06:33Z<p>Liaoj: </p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Completed===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Completed]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=7656Low-power Temperature-insensitive Timer2022-02-21T09:06:12Z<p>Liaoj: </p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Completed]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Analog_Compute-in-Memory_Accelerator_Interface_and_Integration&diff=7350Analog Compute-in-Memory Accelerator Interface and Integration2021-12-06T12:12:31Z<p>Liaoj: </p>
<hr />
<div>[[File:FeFET_ACiM.png|thumb|400px]]<br />
=== Description ===<br />
The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the substantial energy and latency needs of off-chip memories. To tackle this issue, researchers have started investigating on structures base on non-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm.<br />
<br />
One of these most novel and promising devices are the ferroelectric FETs (FeFETs), which exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].<br />
<br />
The target for this project is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system. <br />
In this project the student will:<br />
1. Work in close contact with industry partners for the development of a FeFET IMC crossbar (XBAR) array<br />
2. Design interface for ACiM accelerator<br />
3. Integrate the accelerator with MCU<br />
4. Verify functionality of the system<br />
<br />
===Status: In Progress===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* Worked with at least one RTL language in the past (SystemVerilog or Verilog)<br />
* Prior knowledge of hardware design and computer architecture <br />
* VLSI I<br />
* Knowledge of analog circuit is a plus (e.g. AIC)<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Architecture Design <br />
* 30% RTL implementation<br />
* 30% Verification<br />
<br />
===Professor===<br />
[mailto:tjang@ethz.ch Prof. Taekwang Jang]<br />
<br />
=== Reference===<br />
[1] T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750.<br />
<br />
<br />
[2] T. Soliman et al., "Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 29.2.1-29.2.4, doi: 10.1109/IEDM13553.2020.9372124.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
<!--[[Category:Available]]--><br />
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[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Analog_Compute-in-Memory_Accelerator_Interface_and_Integration&diff=7349Analog Compute-in-Memory Accelerator Interface and Integration2021-12-06T12:07:17Z<p>Liaoj: </p>
<hr />
<div>[[File:FeFET_ACiM.png|thumb|400px]]<br />
=== Description ===<br />
The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the substantial energy and latency needs of off-chip memories. To tackle this issue, researchers have started investigating on structures base on non-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm.<br />
<br />
One of these most novel and promising devices are the ferroelectric FETs (FeFETs), which exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].<br />
<br />
The target for this project is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system. <br />
In this project the student will:<br />
1. Work in close contact with industry partners for the development of a FeFET IMC crossbar (XBAR) array<br />
2. Design interface for ACiM accelerator<br />
3. Integrate the accelerator with MCU<br />
4. Verify functionality of the system<br />
<br />
===Status: In Progress===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* Worked with at least one RTL language in the past (SystemVerilog or Verilog)<br />
* Prior knowledge of hardware design and computer architecture <br />
* VLSI I<br />
* Knowledge of analog circuit is a plus (e.g. AIC)<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Architecture Design <br />
* 30% RTL implementation<br />
* 30% Verification<br />
<br />
===Professor===<br />
[mailto:tjang@ethz.ch Prof. Taekwang Jang]<br />
<br />
=== Reference===<br />
[1] T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750.<br />
<br />
<br />
[2] T. Soliman et al., "Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 29.2.1-29.2.4, doi: 10.1109/IEDM13553.2020.9372124.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
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[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Analog_Compute-in-Memory_Accelerator_Interface_and_Integration&diff=6949Analog Compute-in-Memory Accelerator Interface and Integration2021-09-16T09:54:28Z<p>Liaoj: </p>
<hr />
<div>[[File:FeFET_ACiM.png|thumb|400px]]<br />
=== Description ===<br />
The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the substantial energy and latency needs of off-chip memories. To tackle this issue, researchers have started investigating on structures base on non-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm.<br />
<br />
One of these most novel and promising devices are the ferroelectric FETs (FeFETs), which exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].<br />
<br />
The target for this project is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system. <br />
In this project the student will:<br />
1. Work in close contact with industry partners for the development of a FeFET IMC crossbar (XBAR) array<br />
2. Design interface for ACiM accelerator<br />
3. Integrate the accelerator with MCU<br />
4. Verify functionality of the system<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* Worked with at least one RTL language in the past (SystemVerilog or Verilog)<br />
* Prior knowledge of hardware design and computer architecture <br />
* VLSI I<br />
* Knowledge of analog circuit is a plus (e.g. AIC)<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Architecture Design <br />
* 30% RTL implementation<br />
* 30% Verification<br />
<br />
===Professor===<br />
[mailto:tjang@ethz.ch Prof. Taekwang Jang]<br />
<br />
=== Reference===<br />
[1] T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750.<br />
<br />
<br />
[2] T. Soliman et al., "Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 29.2.1-29.2.4, doi: 10.1109/IEDM13553.2020.9372124.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
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[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:FeFET_ACiM.png&diff=6948File:FeFET ACiM.png2021-09-16T09:53:09Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Analog_Compute-in-Memory_Accelerator_Interface_and_Integration&diff=6947Analog Compute-in-Memory Accelerator Interface and Integration2021-09-16T09:44:48Z<p>Liaoj: Created page with " === Description === The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the..."</p>
<hr />
<div><br />
=== Description ===<br />
The continuous development and use of computation- and memory-intensive algorithms, such as Deep Neural Networks (DNNs) are currently being limited by the substantial energy and latency needs of off-chip memories. To tackle this issue, researchers have started investigating on structures base on non-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm.<br />
<br />
One of these most novel and promising devices are the ferroelectric FETs (FeFETs), which exploit a thin ferroelectric layer between gate and channel to store data [1]. These devices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].<br />
<br />
The target for this project is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system. <br />
In this project the student will:<br />
1. Work in close contact with industry partners for the development of a FeFET IMC crossbar (XBAR) array<br />
2. Design interface for ACiM accelerator<br />
3. Integrate the accelerator with MCU<br />
4. Verify functionality of the system<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* Worked with at least one RTL language in the past (SystemVerilog or Verilog)<br />
* Prior knowledge of hardware design and computer architecture <br />
* VLSI I<br />
* Knowledge of analog circuit is a plus (e.g. AIC)<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Architecture Design <br />
* 30% RTL implementation<br />
* 30% Verification<br />
<br />
===Professor===<br />
[mailto:tjang@ethz.ch Prof. Taekwang Jang]<br />
<br />
=== Reference===<br />
[1] T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750.<br />
<br />
<br />
[2] T. Soliman et al., "Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 29.2.1-29.2.4, doi: 10.1109/IEDM13553.2020.9372124.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
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[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_Time-Encoded_Spiking_Neural_Networks_(IBM-Zurich)&diff=6873Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)2021-08-31T08:54:53Z<p>Liaoj: Created page with "=== Description === Powerful models that rely on artificial neural networks (ANNs) have acquired wide popularity in the last decade. Spiking neural networks (SNNs) represent a..."</p>
<hr />
<div>=== Description ===<br />
Powerful models that rely on artificial neural networks (ANNs) have acquired wide popularity in the last decade. Spiking neural networks (SNNs) represent a very efficient class of neural networks, which communicate through sequences of spikes, thus closely resembling biological neural networks. The spike trains are commonly interpreted as all-or-none signals, corresponding to binary communication with ones and zeros, in which spikes (ones) are sparse and asynchronous, leading to efficient operation.<br />
<br />
Neural encoding deals with determining how information is communicated by electrical signals (action potentials) at the level of individual neurons in SNNs. Fast processing of information is achieved by time encoding methods, where neural communication is based on the precise timing of action potentials, as for example Time-to-First-Spike (TTFS) encoding, where a neuron spikes once when its membrane potential reaches a given threshold, and afterwards it remains silent. TTFS encoding is well suited for low-latency classification algorithms, where the neuron corresponding to the correct class fires first among the top layer neurons.<br />
<br />
We are inviting students to conduct their thesis work (master or bachelor) at IBM Research – Zurich on this exciting topic. The work performed could span hardware design at the circuit level of time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves interactions with several researchers across IBM Research focusing on various aspects of the project.<br />
<br />
===Status: Available===<br />
:Looking for master or bachelor thesis students<br />
If you are interested in this challenging position on an exciting and challenging topic, please send your most recent curriculum vitae including a transcript of grades by email to:<br />
:Dr. Angeliki Pantazi <[mailto:agp@zurich.ibm.com agp@zurich.ibm.com]><br />
<br />
===Prerequisites===<br />
The ideal candidate should have a multi-disciplinary background, strong mathematical aptitude and programming and circuit design skills (analog design on transistor level and/or digital design with VHDL). Prior knowledge of neuromorphic computing concepts is a bonus but not necessary.<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Digital]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Hardware/software_codesign_neural_decoding_algorithm_for_%E2%80%9Cneural_dust%E2%80%9D&diff=6872Hardware/software codesign neural decoding algorithm for “neural dust”2021-08-31T08:38:41Z<p>Liaoj: </p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Non-invasive BMIs, mostly based on EEG signals, do not require surgery to implant sensing nodes in the brain. However, they strongly suffer from low spatial resolution and low signal-to-noise ratio, making them often not accurate. Implantable BMIs, on the other hand, offer high resolution and high signal quality, making them necessary for applications where decoding accuracy is crucial.<br />
<br />
Minimizing the damage to the brain is one of the primary goals of implantable BMI systems. Most of the existing systems are bulky and wired for communication and power transfer. Wireless, miniaturized, and implantable BMI systems (sometimes called “neural recording dust”) hold the promise of restoring motor function while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area.<br />
<br />
Researchers have developed mm-scale neural probe [1][2] and efficient algorithms [3][4] to tackle the problem. Our goal is to hardware/software codesign novel deep learning algorithm for neural decoding based on the spiking band power (SBP) information from the mm-scale neural probe.<br />
<br />
In this project, the student will:<br />
1. Study prior art<br />
2. Get familiar with the dataset and the system<br />
3. Explore ML algorithms (CNNs, RNNs, SNNs, …)<br />
4. H/S codesign efficient algorithms<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[2] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[3] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[4] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
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[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Spiking_Neural_Network_for_Motor_Function_Decoding_Based_on_Neural_Dust&diff=6871Spiking Neural Network for Motor Function Decoding Based on Neural Dust2021-08-31T08:37:53Z<p>Liaoj: </p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Researchers have developed mm-scale implantable neural probe [1][2] aiming to restore motor function while reducing the damage caused by the implantation. Such systems pose stringent constraints on the power consumption, area, and latency.<br />
<br />
Spiking neural network (SNN), an emerging brain-inspired algorithm, takes advantage of asynchronous information and computation to achieve low latency and low power consumption. Unlike images or sounds acquired by conventional sensors, the neural signals are naturally asynchronous and encode information in timing and firing rate, which is perfectly compatible with SNN’s requirement for input data. This makes SNN a good candidate for neural decoding, and the nature of neural signals may release more potential of SNN.<br />
<br />
In particular, reservoir-based Liquid State Machine (LSM) [5] is a recurrent computational model which is a more adequate emulation of the biological cortical networks compared to layer-based SNNs. It maps the input spike trains to the output spike trains by means of the so-called Liquid or reservoir, which consists of a recurrent neural network formed by many computational nodes. Kasabov [6] proposed a reservoir-based SNN, named NeuCube, to learn and understand the spatio-temporal features of the brain activities and has been demonstrated to be competitive to layer-based approaches. A very recent work [7] used NeuCube to perform the regression problem of Grasp-and-Lift dataset achieving very promising results.<br />
<br />
In this project, the student will<br />
<br />
1. Study prior art, including and not limited to LSM, SNN<br />
<br />
2. Get familiar with the dataset, the system, and the deep learning framework<br />
<br />
3. Explore and develop SNN to offline decode finger movement<br />
A more detailed project description will be provided tailored to the type of the project (master or semester).<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[2] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[3] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[4] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[5] W. Maass, et al., “Real-time computing without stable states: A new framework for neural computation based on perturbations”. In Neural Computation 14, 2002, pp. 2531–2560. <br />
<br />
[6] N. K. Kasabov, "NeuCube: A spiking neural network architecture for mapping, learning and understanding of spatio-temporal brain data." Neural Networks 52, 2014, pp. 62-76.<br />
<br />
[7] Kumarasinghe, et al., D. Brain-inspired spiking neural networks for decoding and understanding muscle activity and kinematics from electroencephalography signals during hand movements. Sci Rep 11, 2486 (2021). https://doi.org/10.1038/s41598-021-81805-4<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
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[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Spiking_Neural_Network_for_Motor_Function_Decoding_Based_on_Neural_Dust&diff=6661Spiking Neural Network for Motor Function Decoding Based on Neural Dust2021-07-02T11:38:26Z<p>Liaoj: Created page with "600px === Description === A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and..."</p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Researchers have developed mm-scale implantable neural probe [1][2] aiming to restore motor function while reducing the damage caused by the implantation. Such systems pose stringent constraints on the power consumption, area, and latency.<br />
<br />
Spiking neural network (SNN), an emerging brain-inspired algorithm, takes advantage of asynchronous information and computation to achieve low latency and low power consumption. Unlike images or sounds acquired by conventional sensors, the neural signals are naturally asynchronous and encode information in timing and firing rate, which is perfectly compatible with SNN’s requirement for input data. This makes SNN a good candidate for neural decoding, and the nature of neural signals may release more potential of SNN.<br />
<br />
In particular, reservoir-based Liquid State Machine (LSM) [5] is a recurrent computational model which is a more adequate emulation of the biological cortical networks compared to layer-based SNNs. It maps the input spike trains to the output spike trains by means of the so-called Liquid or reservoir, which consists of a recurrent neural network formed by many computational nodes. Kasabov [6] proposed a reservoir-based SNN, named NeuCube, to learn and understand the spatio-temporal features of the brain activities and has been demonstrated to be competitive to layer-based approaches. A very recent work [7] used NeuCube to perform the regression problem of Grasp-and-Lift dataset achieving very promising results.<br />
<br />
In this project, the student will<br />
<br />
1. Study prior art, including and not limited to LSM, SNN<br />
<br />
2. Get familiar with the dataset, the system, and the deep learning framework<br />
<br />
3. Explore and develop SNN to offline decode finger movement<br />
A more detailed project description will be provided tailored to the type of the project (master or semester).<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[2] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[3] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[4] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[5] W. Maass, et al., “Real-time computing without stable states: A new framework for neural computation based on perturbations”. In Neural Computation 14, 2002, pp. 2531–2560. <br />
<br />
[6] N. K. Kasabov, "NeuCube: A spiking neural network architecture for mapping, learning and understanding of spatio-temporal brain data." Neural Networks 52, 2014, pp. 62-76.<br />
<br />
[7] Kumarasinghe, et al., D. Brain-inspired spiking neural networks for decoding and understanding muscle activity and kinematics from electroencephalography signals during hand movements. Sci Rep 11, 2486 (2021). https://doi.org/10.1038/s41598-021-81805-4<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
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[[Category:Liaoj]]<br />
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[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Hardware/software_codesign_neural_decoding_algorithm_for_%E2%80%9Cneural_dust%E2%80%9D&diff=6607Hardware/software codesign neural decoding algorithm for “neural dust”2021-06-16T18:30:02Z<p>Liaoj: /* Status: Available */</p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Non-invasive BMIs, mostly based on EEG signals, do not require surgery to implant sensing nodes in the brain. However, they strongly suffer from low spatial resolution and low signal-to-noise ratio, making them often not accurate. Implantable BMIs, on the other hand, offer high resolution and high signal quality, making them necessary for applications where decoding accuracy is crucial.<br />
<br />
Minimizing the damage to the brain is one of the primary goals of implantable BMI systems. Most of the existing systems are bulky and wired for communication and power transfer. Wireless, miniaturized, and implantable BMI systems (sometimes called “neural recording dust”) hold the promise of restoring motor function while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area.<br />
<br />
Researchers have developed mm-scale neural probe [1][2] and efficient algorithms [3][4] to tackle the problem. Our goal is to hardware/software codesign novel deep learning algorithm for neural decoding based on the spiking band power (SBP) information from the mm-scale neural probe.<br />
<br />
In this project, the student will:<br />
1. Study prior art<br />
2. Get familiar with the dataset and the system<br />
3. Explore ML algorithms (CNNs, RNNs, SNNs, …)<br />
4. H/S codesign efficient algorithms<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]], [[:User:Adimauro | Alfio Di Mauro]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[2] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[3] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[4] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Hardware/software_codesign_neural_decoding_algorithm_for_%E2%80%9Cneural_dust%E2%80%9D&diff=6600Hardware/software codesign neural decoding algorithm for “neural dust”2021-06-07T14:51:30Z<p>Liaoj: Created page with "600px === Description === A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and..."</p>
<hr />
<div>[[File:ReMote.png|thumb|600px]]<br />
=== Description ===<br />
A brain-machine interface (BMI) acquires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for many neurological diseases, it has won great attention in academia and industry.<br />
<br />
Non-invasive BMIs, mostly based on EEG signals, do not require surgery to implant sensing nodes in the brain. However, they strongly suffer from low spatial resolution and low signal-to-noise ratio, making them often not accurate. Implantable BMIs, on the other hand, offer high resolution and high signal quality, making them necessary for applications where decoding accuracy is crucial.<br />
<br />
Minimizing the damage to the brain is one of the primary goals of implantable BMI systems. Most of the existing systems are bulky and wired for communication and power transfer. Wireless, miniaturized, and implantable BMI systems (sometimes called “neural recording dust”) hold the promise of restoring motor function while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area.<br />
<br />
Researchers have developed mm-scale neural probe [1][2] and efficient algorithms [3][4] to tackle the problem. Our goal is to hardware/software codesign novel deep learning algorithm for neural decoding based on the spiking band power (SBP) information from the mm-scale neural probe.<br />
<br />
In this project, the student will:<br />
1. Study prior art<br />
2. Get familiar with the dataset and the system<br />
3. Explore ML algorithms (CNNs, RNNs, SNNs, …)<br />
4. H/S codesign efficient algorithms<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]], [[:User:xiaywang|Xiaying Wang]]<br />
<br />
===Prerequisites===<br />
* Machine Learning<br />
* Deep Learning<br />
* Python<br />
* VLSI is a plus<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Programming<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] J. Lim et al., “26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, Feb. 2020, pp. 416–418. doi: 10.1109/ISSCC19947.2020.9063005.<br />
<br />
[2] E. Moon et al., “Bridging the ‘Last Millimeter’ Gap of Brain-Machine Interfaces via Near-Infrared Wireless Power Transfer and Data Communications,” ACS Photonics, vol. 8, no. 5, pp. 1430–1438, May 2021, doi: 10.1021/acsphotonics.1c00160.<br />
<br />
[3] S. R. Nason et al., “A low-power band of neuronal spiking activity dominated by local single units improves the performance of brain–machine interfaces,” Nat Biomed Eng, vol. 4, no. 10, pp. 973–983, Oct. 2020, doi: 10.1038/s41551-020-0591-0.<br />
<br />
[4] A. K. Vaskov et al., “Cortical Decoding of Individual Finger Group Motions Using ReFIT Kalman Filter,” Front. Neurosci., vol. 12, 2018, doi: 10.3389/fnins.2018.00751.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:xiaywang]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:ReMote.png&diff=6599File:ReMote.png2021-06-07T14:39:26Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=6598Novel Metastability Mitigation Technique2021-06-07T13:49:53Z<p>Liaoj: </p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=6597Low-power Temperature-insensitive Timer2021-06-07T13:48:55Z<p>Liaoj: </p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=6596Low-power Temperature-insensitive Timer2021-06-07T13:48:06Z<p>Liaoj: </p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=6595Low-power Temperature-insensitive Timer2021-06-07T13:45:45Z<p>Liaoj: /* Reference */</p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Low-power_Temperature-insensitive_Timer&diff=6594Low-power Temperature-insensitive Timer2021-06-07T13:45:28Z<p>Liaoj: Created page with "300px300px === Description === The rapid growth of the internet of things leads to high demand for the cont..."</p>
<hr />
<div>[[File:Timer transient.png|thumb|300px]][[File:timer_circuit.png|thumb|300px]]<br />
=== Description ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. To satisfy the requirement for duty-cycled wireless IoT devices, the timer needs to be precise and low-power. Conventional crystal-based timer is bulky. RC-based timer is a good alternative that can be integrated on-chip [1][2][3]. Capacitors are relatively insensitive to temperature change, so it is critical to control the resistors to achieve temperature-stable timer.<br />
<br />
In this project, the student will:<br />
1. Study prior art <br />
2. Characterizing on-chip resistors<br />
3. Exploring and developing novel on-chip timer<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [[:User:Liaoj | Jiawei Liao]],[mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano]<br />
<br />
===Prerequisites===<br />
* AIC<br />
* VLSI<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 30% Device characterization<br />
* 30% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
[1] T. Jang, M. Choi, S. Jeong, S. Bang, D. Sylvester, and D. Blaauw, “5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016, pp. 102–103. doi: 10.1109/ISSCC.2016.7417927.<br />
[2] G. Cristiano, J. Liao, A. Novello, G. Atzeni, and T. Jang, “A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops,” in 2020 IEEE Symposium on VLSI Circuits, Jun. 2020, pp. 1–2. doi: 10.1109/VLSICircuits18222.2020.9162838.<br />
[3] M. Ding, M. Song, E. Tiurin, S. Traferro, Y.-H. Liu, and C. Bachmann, “A 0.9pJ/cycle 8ppm/oC DFLL-based Wakeup timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing,” p. 2.<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
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[[Category:Liaoj]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Timer_transient.png&diff=6593File:Timer transient.png2021-06-07T13:38:21Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Timer_circuit.png&diff=6592File:Timer circuit.png2021-06-07T13:38:09Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=6591Novel Metastability Mitigation Technique2021-06-07T13:15:29Z<p>Liaoj: </p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: [mailto:giorgio.cristiano@iis.ee.ethz.ch Giorgio Cristiano], [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Novel_Metastability_Mitigation_Technique&diff=6590Novel Metastability Mitigation Technique2021-06-07T11:14:51Z<p>Liaoj: Created page with "300px === Description === Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems..."</p>
<hr />
<div>[[File:Metastability eecis.png|thumb|300px]]<br />
=== Description ===<br />
Modern system-on-a-chip is usually an integration of heterogeneous building blocks. Such heterogeneous systems typically have multiple power and clock domains. Therefore, it is critical to ensure robustness when data cross different power and clock domains.<br />
<br />
Metastability happens when the input signal changes within the setup-hold window around the latching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power consumption. <br />
<br />
The synchronizer is an effective and commonly used method against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passive devices to mitigate the metastability issue.<br />
<br />
===Status: Available===<br />
:Looking for master or semester thesis students<br />
:Supervisor: Giorgio Cristiano<[mailto:giorgio.cristiano@iis.ee.ethz.ch giorgio.cristiano@iis.ee.ethz.ch]>, [[:User:Liaoj | Jiawei Liao]]<br />
<br />
===Prerequisites===<br />
* VLSI<br />
* AIC<br />
<br />
===Character===<br />
* 20% Literature review<br />
* 20% Theory<br />
* 60% Design and simulation<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Digital]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Metastability_eecis.png&diff=6589File:Metastability eecis.png2021-06-07T11:07:08Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Precise_Ultra-low-power_Timer&diff=6537Precise Ultra-low-power Timer2021-05-12T09:19:37Z<p>Liaoj: </p>
<hr />
<div>[[File:LEDonTimer.PNG|thumb|300px]]<br />
[[File:timer_ext_ctrl.PNG|thumb|300px]]<br />
[[File:timer_testboard.PNG|thumb|300px]]<br />
=== Introduction ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operate on the sensor node should be insensitive to temperature variation. Especially for on-chip timers, they have to have high frequency accuracies, meaning that they need to be insensitive to PVT variations and they have to have long-term frequency stability. <br />
<br />
<br />
=== Project Description ===<br />
* Develop a control loop to compensate temperature variation of the on-chip timer.<br />
<br />
===Status: Available===<br />
: Looking for Semester and Master Project Students<br />
: Supervision: [[:User:Liaoj | Jiawei Liao]], Giorgio Cristiano, Hesam Omdeh Ghiasi, Liza Zaper<br />
<br />
===Prerequisites===<br />
* VLSI I<br />
* Solid state device physics will be a plus<br />
<br />
===Professor===<br />
: [https://iis.ee.ethz.ch/people/person-detail.tjang.html Prof. Taekwang Jang] <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:FPGA]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=LED_on_Timer:_On-chip_Oscillator_Tuned_by_Light_to_Compensate_Temperature_Variation&diff=6536LED on Timer: On-chip Oscillator Tuned by Light to Compensate Temperature Variation2021-05-12T09:05:15Z<p>Liaoj: Liaoj moved page LED on Timer: On-chip Oscillator Tuned by Light to Compensate Temperature Variation to Precise Ultra-low-power Timer</p>
<hr />
<div>#REDIRECT [[Precise Ultra-low-power Timer]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Precise_Ultra-low-power_Timer&diff=6535Precise Ultra-low-power Timer2021-05-12T09:05:14Z<p>Liaoj: Liaoj moved page LED on Timer: On-chip Oscillator Tuned by Light to Compensate Temperature Variation to Precise Ultra-low-power Timer</p>
<hr />
<div>[[File:LEDonTimer.PNG|thumb|300px]]<br />
[[File:timer_ext_ctrl.PNG|thumb|300px]]<br />
[[File:timer_testboard.PNG|thumb|300px]]<br />
=== Introduction ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operate on the sensor node should be insensitive to temperature variation. Especially for on-chip timers, they have to have high frequency accuracies, meaning that they need to be insensitive to PVT variations and they have to have long-term frequency stability. <br />
While the temperature influences the characteristic of MOSFET, the light can also have similar impact, for instance, on the threshold voltage. This gives us the opportunity to compensate the temperature-dependent variations by tuning light. <br />
<br />
=== Project Description ===<br />
The goal of the project is to explore the impact of light on transistors and on-chip resistors with both theory and experiments. Eventually, with the obtained knowledge, an off-chip FPGA-based control loop can be developed to compensate the temperature variation for an on-chip timer. Students will:<br />
* Study literature about light and thermal impact on MOSFET.<br />
* Carry out the measurement for light and thermal impact on MOSFET characteristics.<br />
* Develop a control loop to compensate temperature variation of the on-chip timer.<br />
<br />
===Status: Available===<br />
: Looking for Semester and Master Project Students<br />
: Supervision: [[:User:Liaoj | Jiawei Liao]], Giorgio Cristiano, Hesam Omdeh Ghiasi, Liza Zaper<br />
<br />
===Prerequisites===<br />
* VLSI I<br />
* Solid state device physics will be a plus<br />
<br />
===Professor===<br />
: [https://iis.ee.ethz.ch/people/person-detail.tjang.html Prof. Taekwang Jang] <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:FPGA]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Precise_Ultra-low-power_Timer&diff=6244Precise Ultra-low-power Timer2021-01-18T22:30:35Z<p>Liaoj: </p>
<hr />
<div>[[File:LEDonTimer.PNG|thumb|300px]]<br />
[[File:timer_ext_ctrl.PNG|thumb|300px]]<br />
[[File:timer_testboard.PNG|thumb|300px]]<br />
=== Introduction ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operate on the sensor node should be insensitive to temperature variation. Especially for on-chip timers, they have to have high frequency accuracies, meaning that they need to be insensitive to PVT variations and they have to have long-term frequency stability. <br />
While the temperature influences the characteristic of MOSFET, the light can also have similar impact, for instance, on the threshold voltage. This gives us the opportunity to compensate the temperature-dependent variations by tuning light. <br />
<br />
=== Project Description ===<br />
The goal of the project is to explore the impact of light on transistors and on-chip resistors with both theory and experiments. Eventually, with the obtained knowledge, an off-chip FPGA-based control loop can be developed to compensate the temperature variation for an on-chip timer. Students will:<br />
* Study literature about light and thermal impact on MOSFET.<br />
* Carry out the measurement for light and thermal impact on MOSFET characteristics.<br />
* Develop a control loop to compensate temperature variation of the on-chip timer.<br />
<br />
===Status: Available===<br />
: Looking for Semester and Master Project Students<br />
: Supervision: [[:User:Liaoj | Jiawei Liao]], Giorgio Cristiano, Hesam Omdeh Ghiasi, Liza Zaper<br />
<br />
===Prerequisites===<br />
* VLSI I<br />
* Solid state device physics will be a plus<br />
<br />
===Professor===<br />
: [https://iis.ee.ethz.ch/people/person-detail.tjang.html Prof. Taekwang Jang] <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:FPGA]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Timer_ext_ctrl.PNG&diff=6243File:Timer ext ctrl.PNG2021-01-18T22:27:02Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:Timer_testboard.PNG&diff=6242File:Timer testboard.PNG2021-01-18T22:26:42Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=File:LEDonTimer.PNG&diff=6241File:LEDonTimer.PNG2021-01-18T22:16:16Z<p>Liaoj: </p>
<hr />
<div></div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Precise_Ultra-low-power_Timer&diff=6240Precise Ultra-low-power Timer2021-01-18T22:10:44Z<p>Liaoj: Created page with "=== Introduction === The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operat..."</p>
<hr />
<div>=== Introduction ===<br />
The rapid growth of the internet of things leads to high demand for the continuous monitoring of environmental and biomedical signals. The circuits operate on the sensor node should be insensitive to temperature variation. Especially for on-chip timers, they have to have high frequency accuracies, meaning that they need to be insensitive to PVT variations and they have to have long-term frequency stability. <br />
While the temperature influences the characteristic of MOSFET, the light can also have similar impact, for instance, on the threshold voltage. This gives us the opportunity to compensate the temperature-dependent variations by tuning light. <br />
<br />
=== Project Description ===<br />
The goal of the project is to explore the impact of light on transistors and on-chip resistors with both theory and experiments. Eventually, with the obtained knowledge, an off-chip FPGA-based control loop can be developed to compensate the temperature variation for an on-chip timer. Students will:<br />
* Study literature about light and thermal impact on MOSFET.<br />
* Carry out the measurement for light and thermal impact on MOSFET characteristics.<br />
* Develop a control loop to compensate temperature variation of the on-chip timer.<br />
<br />
===Status: Available===<br />
: Looking for Semester and Master Project Students<br />
: Supervision: [[:User:Liaoj | Jiawei Liao]], Giorgio Cristiano, Hesam Omdeh Ghiasi, Liza Zaper<br />
<br />
===Prerequisites===<br />
* VLSI I<br />
* Solid state device physics will be a plus<br />
<br />
===Professor===<br />
: [https://iis.ee.ethz.ch/people/person-detail.tjang.html Prof. Taekwang Jang] <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
[[#top|↑ top]]<br />
[[Category:EECIS]]<br />
[[Category:Available]]<br />
[[Category:2021]]<br />
[[Category:Liaoj]]<br />
[[Category:Group Work]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:FPGA]]</div>Liaojhttp://iis-projects.ee.ethz.ch/index.php?title=Exploring_feature_selection_and_classification_algorithms_for_ultra-low-power_closed-loop_systems_for_epilepsy_control&diff=6239Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control2021-01-18T21:16:07Z<p>Liaoj: </p>
<hr />
<div>[[File:Ieeg seizure.png|thumb|300px]][[File:EpilepsyStim.jpg|thumb|300px]]<br />
=== Introduction ===<br />
The usage of Implantable Medical Devices (IMD) as therapeutic systems is gaining acceptance in the medical community and from patients. Following this trend and taking benefit of improvements in microelectronic fabrication technologies, new systems are proposed. The complexity of the microelectronic implantable systems has significantly increased over the years, constituting true systems-on-a-chip, that gather functionalities including electrical recording and stimulation, data pre-processing, wireless power and data transfer and overall system control. Data is generally processed inside the implant in the digital domain. The major goal consists of reliably detecting some markers of an abnormal signal that allows tailoring a therapy that is to be delivered in a closed-loop manner. <br />
The most widely used method and data processing chain involves recording of electrical signals, converting them into the digital domain, detecting some features and their relative intensities, and subsequently controlling electrical stimulation. The effectiveness of the delivered therapy is verified in real time. This technique is used in the control of epilepsy in closed-loop fashion, for example. Still, improving the efficiency of the detection is a key factor to the success of the therapy.<br />
<br />
=== Project Description ===<br />
The goal of this project is to optimize the feature selection algorithm and develop a more accurate and light-weight seizure detection algorithm. To this end, students will:<br />
* Study literature about seizure detection and feature selection<br />
* Optimize feature selection algorithms<br />
* Implement machine learning algorithms for seizure detection based on the selected features. Both traditional machine learning and deep learning algorithms can be explored.<br />
* Test on iEEG dataset<br />
<br />
<br />
===Status: Available===<br />
:Looking for Semester and Master Project Students<br />
:Supervision: [[:User:Liaoj | Jiawei Liao]], [[:User:Herschmi | Michael Hersche]], Reza Ranjandish <br />
===Prerequisites===<br />
* Machine Learning<br />
* Python Programming<br />
===Character===<br />
* 20% literature review<br />
* 40% Feature selection algorithm optimization <br />
* 40% Seizure detection algorithm development<br />
<br />
===Professor===<br />
Prof. Taekwang Jang <[mailto:tjang@ethz.ch tjang@ethz.ch]><br />
<br />
=== Reference===<br />
<br />
<br />
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---></div>Liaoj