http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Pullinia&feedformat=atomiis-projects - User contributions [en]2024-03-28T23:00:18ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2151Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T18:33:00Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Architectural diagram with Pre-Processing IP]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The hw IP will need to be as much as possible usable by different processing algorithms to maintain as much as possible the general purpouse phylosofy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between hw and sw in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini]], [[:User:schaffner|Michael Schaffner]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2150Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T18:31:49Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Sample Preprocessing]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The hw IP will need to be as much as possible usable by different processing algorithms to maintain as much as possible the general purpouse phylosofy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between hw and sw in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini]], [[:User:schaffner|Michael Schaffner]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2091Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T15:24:40Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Architectural Diagram with Preprocessing IP]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The HW IP will need to be as much as possible usable with different processing algorithms to maintain as much as possible the general purpose philosophy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between HW and SW in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2090Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T15:20:04Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap preprocIP.png|400px|thumb|right|Sample Preprocessing]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The hw IP will need to be as much as possible usable by different processing algorithms to maintain as much as possible the general purpouse phylosofy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between hw and sw in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Audio_Video_Preprocessing_In_Parallel_Ultra_Low_Power_Platform&diff=2089Audio Video Preprocessing In Parallel Ultra Low Power Platform2016-04-14T15:18:57Z<p>Pullinia: Created page with "==Short Description== Sample Preprocessing Sample Preprocessing Audio and video processing ..."</p>
<hr />
<div>==Short Description==<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
[[File:Ap signals.png|400px|thumb|right|Sample Preprocessing]]<br />
Audio and video processing on embedded systems has many constraints coming from the fewer available resources. In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming from the sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases,could be done very efficiently in hw reducing significantly the load on the CPU. Potential candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression. The hw IP will need to be as much as possible usable by different processing algorithms to maintain as much as possible the general purpouse phylosofy of the whole system.<br />
<br />
The goal of this project is to evaluate the best trade off between hw and sw in the preprocessing step for few A/V processing algorithms<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% HW Design<br />
<br />
===Requirements===<br />
: Matlab<br />
: Good C programming skills<br />
: Knowledge of digital circuit design<br />
: Knowledge of at least one HDL(VHDL, Verilog, SystemVerilog)<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2088Fast Wakeup From Deep Sleep State2016-04-14T15:04:02Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
*Implement SW based save/restore<br />
*Extend the current debug unit and make it memory mapped<br />
*Control system DMA to save/restore L1 data memory<br />
*Dump core state to memory via debug unit<br />
*Validate the design and compare with SW solution<br />
*Power estimation<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=User:Pullinia&diff=2087User:Pullinia2016-04-14T15:01:30Z<p>Pullinia: /* Interests */</p>
<hr />
<div>==Antonio Pullini==<br />
<br />
==Interests==<br />
* Low Power<br />
* Digital Design<br />
<br />
==Contact Information==<br />
* '''Office''': ETZ J68.1<br />
* '''e-mail''': [mailto:pullinia@ee.ethz.ch pullinia@iis.ee.ethz.ch]<br />
* '''phone''': (+41 44 63) 266 74<br />
* '''www''': [http://asic.ethz.ch/cg/authors/Antonio_Pullini.html Chip Gallery Webpage]<br />
[[Category:Supervisors]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2085Fast Wakeup From Deep Sleep State2016-04-14T15:00:13Z<p>Pullinia: Pullinia moved page Fast Wakeup to Fast Wakeup From Deep Sleep State</p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
-Implement SW based save/restore<br />
-Extend the current debug unit and make it memory mapped<br />
-Control system DMA to save/restore L1 data memory<br />
-Dump core state to memory via debug unit<br />
-Validate the design<br />
-Power estimation<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup&diff=2086Fast Wakeup2016-04-14T15:00:13Z<p>Pullinia: Pullinia moved page Fast Wakeup to Fast Wakeup From Deep Sleep State</p>
<hr />
<div>#REDIRECT [[Fast Wakeup From Deep Sleep State]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2083Fast Wakeup From Deep Sleep State2016-04-14T14:54:29Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
-Implement SW based save/restore<br />
-Extend the current debug unit and make it memory mapped<br />
-Control system DMA to save/restore L1 data memory<br />
-Dump core state to memory via debug unit<br />
-Validate the design<br />
-Power estimation<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2082Fast Wakeup From Deep Sleep State2016-04-14T14:49:34Z<p>Pullinia: </p>
<hr />
<div>==Short Description==<br />
[[File:Ap iot pattern.png|400px|thumb|right|Typical IoT power cycle]]<br />
[[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
-Extend the current debug unit and enable its access from the system interconnect<br />
-implement a state machine that controls the system DMA to save/restore data stored in L1 data memory<br />
-design the controller to save and restore both core and L1 memory.<br />
-validate the design and include save/restore checks in the regression infrastructure<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 20% Embedded programming<br />
: 40% HW design<br />
: 40% System validation<br />
<br />
===Requirements===<br />
Knowledge of C/C++<br />
VHDL or Verilog HDL<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Fast_Wakeup_From_Deep_Sleep_State&diff=2081Fast Wakeup From Deep Sleep State2016-04-14T14:45:09Z<p>Pullinia: Created page with "==Short Description== Architecture with reusable IPs highlighted Ultra-low power operation and extreme energy efficiency are str..."</p>
<hr />
<div>==Short Description==<br />
[[File:Ap fulmine arch.png|600px|thumb|right|Architecture with reusable IPs highlighted]]<br />
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.<br />
Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery.<br />
The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components.<br />
The project can be summarized as follows:<br />
1-Extend the current debug unit and enable its access from the system interconnect<br />
2-implement a state machine that controls the system DMA to save/restore data stored in L1 data memory<br />
3-design the controller to save and restore both core and L1 memory.<br />
4-validate the design and include save/restore checks in the regression infrastructure<br />
<br />
===Status: Available ===<br />
: Semester/Master Thesis<br />
: Supervision: [[:User:Pullinia|Antonio Pullini (IIS)]]<br />
===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
===Character===<br />
: 60% Theory, Algorithms and Simulation<br />
: 40% VHDL<br />
<br />
===Requirements===<br />
Knowledge of matlab and/or C/C++<br />
VHDL<br />
<br />
==Links== <br />
<br />
[[#top|? top]]<br />
<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]</div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=File:Ap_signals.png&diff=2079File:Ap signals.png2016-04-14T14:37:09Z<p>Pullinia: </p>
<hr />
<div></div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=File:Ap_iot_pattern.png&diff=2077File:Ap iot pattern.png2016-04-14T14:35:16Z<p>Pullinia: </p>
<hr />
<div></div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=File:Ap_preprocIP.png&diff=2074File:Ap preprocIP.png2016-04-14T14:33:21Z<p>Pullinia: </p>
<hr />
<div></div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=File:Ap_fulmine_arch.png&diff=2072File:Ap fulmine arch.png2016-04-14T14:32:22Z<p>Pullinia: </p>
<hr />
<div></div>Pulliniahttp://iis-projects.ee.ethz.ch/index.php?title=Hardware_Support_for_IDE_in_Multicore_Environment&diff=465Hardware Support for IDE in Multicore Environment2014-03-25T10:13:48Z<p>Pullinia: Created page with "thumb ==Short Description== Abstract of the project ===Status: Available === : Looking for 1-2 Semester/Master students : C..."</p>
<hr />
<div>[[File:Hardware support for IDE in multicore.jpg|thumb]]<br />
==Short Description==<br />
Abstract of the project<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester/Master students<br />
: Contact: [[:User:Pullinia | Antonio Pullini]]<br />
===Prerequisites===<br />
: VLSI I<br />
: VLSI II (''recommended'')<br />
<!-- <br />
===Status: Completed ===<br />
: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
---><br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: [[:User:Mluisier | Mathieu Luisier]]<br />
---><br />
===Character===<br />
: 40% Hardware Design<br />
: 40% EDA tools<br />
: 20% Testing<br />
<br />
===Professor===<br />
[http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
<br />
[[#top|↑ top]]<br />
==Detailed Task Description==<br />
<br />
===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
<br />
==Results== <br />
<br />
==Links== <br />
[[Category:Pulp]]<br />
[[Category:Digital]]<br />
[[Category:Available]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
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COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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[[Category:Nano Electronics]]<br />
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[[Category:In progress]]<br />
[[Category:Completed]]<br />
[[Category:Hot]]<br />
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TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
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NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
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[[Category:2010]]<br />
[[Category:2011]]<br />
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[[Category:2014]]<br />
<br />
---></div>Pullinia