http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Tbenz&feedformat=atomiis-projects - User contributions [en]2024-03-28T21:21:34ZUser contributionsMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Taping_a_Safer_Silicon_Implementation_of_Snitch_(M/2-3S)&diff=9952Taping a Safer Silicon Implementation of Snitch (M/2-3S)2023-11-24T16:47:53Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Reserved]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Master / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
We recently started testing Occamy, our massive 434-core general-purpose compute accelerator based on the Snitch architecture. We can successfully run code on the two Linux-capable cores and on the 432 Snitch cores.<br />
However, we have identified some dangerous design practices that could have ended Occamy if we had not had any failsafe mechanisms in place. We want to understand these issues in more detail and fix them to make further tapeouts safer. <br />
<br />
= Project =<br />
In this project, you will certainly investigate and implement/improve the following design aspects:<br />
* Simplified cluster-local and bypassable bootrom<br />
* Safer implementation of WFI<br />
* Making the Snitch core debuggable with GDB<br />
* Remove all non-resettable flip-flops<br />
* Pushing the parameterization of the cluster to the limit: Is a single-core cluster possible?<br />
* Improving on of our FLL IPs<br />
* Adding features that ease debugging on the ASIC tester, e.g., creating an FLL-observation unit.<br />
<br />
You will then verify these changes on an FPGA or in a post-layout simulation before taping a Snitch system with your changes. During your project, you will be able to run real workloads on Occamy to understand better the issues mentioned above. <br />
<br />
== Character ==<br />
<br />
* 20% Study Snitch, evaluate the issues on Occamy<br />
* 20% Design, implementation, and verification of your changes<br />
* 60% Tapeout a Snitch-based system<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in computer architecture<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Visited/visiting VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Scaleout_Study_on_Interleaved_Memory_Transfers_in_Huge_Manycore_Systems_with_Multiple_HBM_Channels_(M/1-3S)&diff=9853Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)2023-11-03T09:18:43Z<p>Tbenz: Created page with "<!-- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --> Category:Digital Category:High Performance SoCs [..."</p>
<hr />
<div><!-- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Fischeti]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Master / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
Today's systems are massively scaled out over huge spans of silicon or even over multiple dies. These systems usually no longer have a single memory controller (DDR5/HBM) but rather feature multiple and distributed memory controllers. This distribution of controllers makes the physical design and the interconnect of these systems easier but at the cost of a more complex data layout. To reach full throughput, the data must be distributed (e.g., interleaved) over multiple channels. <br />
<br />
At IIS, we are working on a latency-tolerant DMA unit that supports transactions to multiple endpoints simultaneously. We recently created an initial draft support for memory interleaving directly within this DMA unit (the unit will do the interleaved accesses automatically and transparently to the user).<br />
<br />
= Project =<br />
In this project, you will take this draft of the DMA and finalize it. You will also evaluate the scalability of this approach by creating systems with a configurable amount of endpoints, DMA engines, and various on-chip network topologies (including off-chip die-to-die links).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA and Snitch<br />
* 20% Finalizing the support for interleaved accesses<br />
* 60% Evaluation of the approach on different configurations with different benchmarks<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems and computer architecture<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Taping_a_Safer_Silicon_Implementation_of_Snitch_(M/2-3S)&diff=9852Taping a Safer Silicon Implementation of Snitch (M/2-3S)2023-11-03T08:53:59Z<p>Tbenz: /* Status: Available */</p>
<hr />
<div><!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Master / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
We recently started testing Occamy, our massive 434-core general-purpose compute accelerator based on the Snitch architecture. We can successfully run code on the two Linux-capable cores and on the 432 Snitch cores.<br />
However, we have identified some dangerous design practices that could have ended Occamy if we had not had any failsafe mechanisms in place. We want to understand these issues in more detail and fix them to make further tapeouts safer. <br />
<br />
= Project =<br />
In this project, you will certainly investigate and implement/improve the following design aspects:<br />
* Simplified cluster-local and bypassable bootrom<br />
* Safer implementation of WFI<br />
* Making the Snitch core debuggable with GDB<br />
* Remove all non-resettable flip-flops<br />
* Pushing the parameterization of the cluster to the limit: Is a single-core cluster possible?<br />
* Improving on of our FLL IPs<br />
* Adding features that ease debugging on the ASIC tester, e.g., creating an FLL-observation unit.<br />
<br />
You will then verify these changes on an FPGA or in a post-layout simulation before taping a Snitch system with your changes. During your project, you will be able to run real workloads on Occamy to understand better the issues mentioned above. <br />
<br />
== Character ==<br />
<br />
* 20% Study Snitch, evaluate the issues on Occamy<br />
* 20% Design, implementation, and verification of your changes<br />
* 60% Tapeout a Snitch-based system<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in computer architecture<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Visited/visiting VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Taping_a_Safer_Silicon_Implementation_of_Snitch_(M/2-3S)&diff=9851Taping a Safer Silicon Implementation of Snitch (M/2-3S)2023-11-03T08:52:42Z<p>Tbenz: Created page with "<!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:..."</p>
<hr />
<div><!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
We recently started testing Occamy, our massive 434-core general-purpose compute accelerator based on the Snitch architecture. We can successfully run code on the two Linux-capable cores and on the 432 Snitch cores.<br />
However, we have identified some dangerous design practices that could have ended Occamy if we had not had any failsafe mechanisms in place. We want to understand these issues in more detail and fix them to make further tapeouts safer. <br />
<br />
= Project =<br />
In this project, you will certainly investigate and implement/improve the following design aspects:<br />
* Simplified cluster-local and bypassable bootrom<br />
* Safer implementation of WFI<br />
* Making the Snitch core debuggable with GDB<br />
* Remove all non-resettable flip-flops<br />
* Pushing the parameterization of the cluster to the limit: Is a single-core cluster possible?<br />
* Improving on of our FLL IPs<br />
* Adding features that ease debugging on the ASIC tester, e.g., creating an FLL-observation unit.<br />
<br />
You will then verify these changes on an FPGA or in a post-layout simulation before taping a Snitch system with your changes. During your project, you will be able to run real workloads on Occamy to understand better the issues mentioned above. <br />
<br />
== Character ==<br />
<br />
* 20% Study Snitch, evaluate the issues on Occamy<br />
* 20% Design, implementation, and verification of your changes<br />
* 60% Tapeout a Snitch-based system<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in computer architecture<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Visited/visiting VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_an_At-memory_Low-overhead_Bufferless_Matrix_Transposition_Accelerator_(1-3S/B)&diff=9845Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)2023-11-03T08:27:45Z<p>Tbenz: Created page with "<!-- Creating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C..."</p>
<hr />
<div><!-- Creating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g., transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (inside of iDMA) using the already present cluster TCDM as its buffer.<br />
<br />
The resulting stream accelerators are extremely lightweight yet very performant.<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. Finally, you evaluate your approach compared to accelerators using a dedicated internal buffer. Depending on the progress, this work can directly lead to a publication.<br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9844Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-11-03T08:25:39Z<p>Tbenz: Blanked the page</p>
<hr />
<div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Evaluating_The_Use_of_Snitch_In_The_PsPIN_RISC-V_In-network_Accelerator_(M)&diff=9843Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)2023-11-03T08:24:43Z<p>Tbenz: /* Project */</p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
The SPCL group is working on PsPIN [1], an implementation of the sPIN programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP cluster to perform the calculations. We would now investigate if package processing could further be accelerated if we are using the Snitch [4] infrastructure.<br />
<br />
<br />
= Project =<br />
In this project, you will update the PULP implementation of sPIN (PsPIN) to the newest version of the PULP cluster, optimizing the sPIN extensions in the process. You then integrate Snitch, creating SsPIN. Finally, you will evaluate the advantages and disadvantages of either implementation on an FPGA and synthesizing them in an advanced GF12 node.<br />
<br />
This project will directly lead to a publication. <br />
<br />
== Character ==<br />
<br />
* 20% Getting used to PsPIN and updating the PULP cluster to the most recent version<br />
* 40% Implementing Snitch-based in-network accelerator, creating SsPIN<br />
* 40% Evaluating both versions, comparing them quantitatively<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-pspin"><br />
[1] “Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021..” https://ieeexplore.ieee.org/iel7/12/9821023/09522037.pdf<br />
</div><br />
<div id="ref-spin><br />
[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. "sPIN: High-performance streaming Processing in the Network." In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.<br />
</div><br />
<div id="ref-pulp"><br />
[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. "PULP: A parallel ultra-low power platform for next generation IoT applications." In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.<br />
</div><br />
<div id="ref-snitch"><br />
[4] F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.” 2020.<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_and_Implementation_of_a_Fully-digital_Platform-independent_Integrated_Temperature_Sensor_Enabling_DVFS_in_Open-source_Tapeouts_(1-3S/B)&diff=9842Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)2023-11-03T08:21:53Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:ASIC]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Aottaviano]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Aottaviano | Alessandro Ottaviano]]: [mailto:aottaviano@iis.ee.ethz.ch aottaviano@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
The performance and energy-consumption of integrated devices depend on the temperature of their active region. Measuring this temperature through the package is very difficult to achieve. <br />
Integrating temperature probes directly into the active region solves this issue.<br />
<br />
= Project =<br />
You create an all-digital temperature probe as well as its controlling and interfacing circuit. You will then proceed to harden it in both TSMC65 (closed-source flow) and SKY130 (open-source flow). You will fabricate your design integrated into a larger SoC tapeout.<br />
<br />
== Character ==<br />
<br />
* 30% Deicing means of measuring the temperature<br />
* 40% Implementing (and hardening) the probe as well as the interface circuit<br />
* 30% Integration into a large SoC tapeout.<br />
<br />
== Prerequisites ==<br />
<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Completed VLSI II or visiting VLSI II in parallel with the thesis<br />
* Preferred: VLSI III.<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Towards_Formal_Verification_of_the_iDMA_Engine_(1-3S/B)&diff=9841Towards Formal Verification of the iDMA Engine (1-3S/B)2023-11-03T08:21:18Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Towards Formal Verification of the iDMA Engine (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Michaero]]<br />
[[Category:Paulsc]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we have created a high-performance DMA Engine called iDMA. So far we have verified the unit's correctness using a simple file-based System-Verilog testbench. <br />
<br />
Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy. One approach is [https://en.wikipedia.org/wiki/Formal_verification formal verification], where the function of a circuit is compared against a set of mathematically formulated properties. In the case of the iDMA we could formulate e.g. deadlock-free operation and verify if the hardware has this property.<br />
<br />
At IIS we have both industry-grade and free-and-open-source tools to do the formal verification process.<br />
<br />
= Project =<br />
In this project, you use formal verification to prove some properties of the iDMA ensuring its correct operation.<br />
<br />
== Character ==<br />
<br />
* 20% Getting started with formal verification and the tools used<br />
* 60% Implementing and verifying a given set of properties<br />
* 20% Improving the RTL should bug(s) be present<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_a_Free_and_Open-Source_Verification_Environment_for_Our_New_DMA_Engine_(1-3S/B)&diff=9840Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)2023-11-03T08:21:02Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Michaero]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we have created a high-performance DMA Engine called iDMA. So far we have verified the unit's correctness using a simple file-based System-Verilog testbench. <br />
<br />
Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy that:<br />
* Only uses free-and-open-source tools (Verilator) to simulate the iDMA or uses UVM-based verification elements in QuestaSim<br />
* Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...)<br />
<br />
= Project =<br />
In this project, you develop a verification environment around our iDMA Engine.<br />
<br />
== Character ==<br />
<br />
* 30% Planning and design of the test environment<br />
* 50% Implementing a new testbench<br />
* 20% Verification of / Improving the testbench<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of C/C++, should Verilator be targetted<br />
* Preferred: Knowledge of AXI4<br />
* Preferred: Experience with Verilator<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=IP-Based_SoC_Generation_and_Configuration_(1-3S/B)&diff=9839IP-Based SoC Generation and Configuration (1-3S/B)2023-11-03T08:19:25Z<p>Tbenz: </p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Paulsc]]<br />
[[Category:Tbenz]]<br />
[[Category:Nwistoff]]<br />
[[Category:Available]]<br />
<br />
== Introduction ==<br />
<br />
At IIS, we often tape out systems-on-chip (SoCs) with new hardware configurations and small-scale hardware extensions to evaluate their impact. Moving to more complex SoCs, top-level connectivity and parameterization become a major design issue:<br />
<br />
* Each SoC will share many of the same IPs, but have its own top-level design, creating numerous design variants which are hard to maintain.<br />
* Manually managing connection and parametrization of IPs is the norm, but becomes more difficult and error-prone the larger the system becomes.<br />
* ''Design exploration is severely impeded'' by the effort of manually instantiating all top-level SoC modules and configuring them individually in various packages.<br />
<br />
This increasingly time-consuming tedium to ensure the SoC is properly parametrized and connected is fittingly referred to as ''top-level hell''.<br />
<br />
An industry-standard approach to tackle this issue is ''High-level Synthesis'' (HLS), for example using SystemC, Chisel [https://www.chisel-lang.org/], or Spinal HDL [https://spinalhdl.github.io/SpinalDoc-RTD/]. However, this approach introduces significant drawbacks:<br />
<br />
* ''All RTL is generated'', taking control from the designers to adapt and optimize it and leaving them exposed to possible generation bugs.<br />
* Unlike hand-written code, the generated RTL is ''neither readable nor interpretable'', making debugging in simulation and implementation difficult to impossible.<br />
* The ''designers lose control'' over clock gating, power gating (which has to be inserted manually), and certainty in applying targeted design constraints.<br />
<br />
At IIS, we focus on creating highly-optimized, interoperable core and SoC IPs. Ideally, we want to assemble SoCs from these IPs by ''connecting and configuring them automatically'' instead of generating suboptimal, intransparent RTL with HLS.<br />
<br />
Recently, we created a script-based tool called ''Solder'', which combines a bunch of templated snippets to connect IP instantiations to a top level in a comprehensive, human-readable way. However, Solder is currently tied to a specific environment, barely configurable, and incapable of optimizing hardware configurations automatically.<br />
<br />
== Project ==<br />
<br />
In this project, you will '''improve on our SoC generation and configuration stack''' using Solder through:<br />
<br />
* '''Generalization''': Currently, Solder is simply a loose collection of scripts and templates shipped with the Snitch system [https://github.com/pulp-platform/snitch]. You will<br />
** Turn it into a standalone tool independent of the Snitch source tree which can be used with any System/IPs and a number of protocols<br />
** Make it fully configurable and extensible through per-IP maniftests and a top-level configuration.<br />
* '''Demonstration''': You will use this new standalone tool to generate the top level of a representative SoC from existing IPs.<br />
<br />
Depending on our interests and the time remaining, the following tasks can also be tackled:<br />
<br />
* '''QoR Estimation''': You can use the information of the configured top-level and IPs to estimate key figures of merit without sythesizing or simulating the hardware, such as area, latency, throughput, and possibly power.<br />
* '''Optimization''': You can use your estimations to automatically optimize your SoC configuration given certain constraints, greatly simplifying SoC design and exploration.<br />
* '''Secondary output generation''': Like the existing scripts, you can generate additional outputs from your unified SoC view such as address maps, header files, and linker scripts among others.<br />
<br />
== Requirements ==<br />
<br />
* Experience with software development (''not'' only ML) in Python<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferably: previous experience with or exposure to SoC design or architecture<br />
* Preferably: previous experience with templating engines such as Mako<br />
<br />
==Composition==<br />
<br />
* 10% Code review<br />
* 20% Software architecture planning<br />
* 50% Implementation<br />
* 20% Evaluation<br />
<br />
== Project Supervisors ==<br />
* [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
* [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
* [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Boundry_Scan_Generator_(1-3S/B/2-3G)&diff=9838Creating A Boundry Scan Generator (1-3S/B/2-3G)2023-11-03T07:55:02Z<p>Tbenz: </p>
<hr />
<div><!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Reserved]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
When testing more complex ASICs in intricate packages, the JTAG boundary scan becomes a valuable tool to debug connectivity issues. Unfortunately, we currently have no way to generate the simple hardware required to implement the boundary scan in an arbitrary ASIC.<br />
<br />
= Project =<br />
You will create a tool that generates and inserts the required hardware around an existing ASIC design. Your generator should also create a testbench and the patterns for our ASIC tester to facilitate both verification and the actual testing of your boundary hardware. <br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study JTAG standard<br />
* 40% Design, implementation, and verification of the generator<br />
* 40% Implement your boundary scan hardware in an existing ASIC (and retape it)<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9837Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-11-03T07:46:43Z<p>Tbenz: /* Introduction */</p>
<hr />
<div><!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g., transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (based on iDMA) which is instead using the cluster TCDM as its buffer. This new unit would not only copy the data stream in a linear fashion but calculate configurable memory patterns to reorganize the data.<br />
<br />
The resulting stream accelerators are extremely lightweight yet very performant.<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. Finally, you evaluate your approach compared to accelerators using a dedicated internal buffer. Depending on the progress, this work can directly lead to a publication.<br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9836Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-11-03T07:45:11Z<p>Tbenz: /* Project */</p>
<hr />
<div><!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g., transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (based on iDMA) which is instead using the cluster TCDM as its buffer.<br />
<br />
The resulting stream accelerators are extremely lightweight yet very performant.<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. Finally, you evaluate your approach compared to accelerators using a dedicated internal buffer. Depending on the progress, this work can directly lead to a publication.<br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9835Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-11-03T07:44:13Z<p>Tbenz: /* Introduction */</p>
<hr />
<div><!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g., transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (based on iDMA) which is instead using the cluster TCDM as its buffer.<br />
<br />
The resulting stream accelerators are extremely lightweight yet very performant.<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. You then finally evaluate your approach compared to accelerators using a dedicated internal buffer. <br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Modeling_High_Bandwidth_Memory_for_Rapid_Design_Space_Exploration_(1-3S/B)&diff=9834Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)2023-11-03T07:39:07Z<p>Tbenz: </p>
<hr />
<div><!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis <br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
<br />
We recently taped Occamy in 12nm featuring a High Bandwidth Memory (HBM) controller. Simulations of the chip with the HBM active require multiple orders of magnitude more time than a regular RTL-only simulation due to the complexity of the HBM subsystem.<br />
<br />
= Project =<br />
<br />
We would like to characterize the HBM subsystem, gaining key figures of merits like throughput, latency, etc. in the process. We then use these numbers to create a simple simulation-only (or RTL unit) that mimics the behavior of HBM but operates much faster in simulation.<br />
<br />
<br />
== Character ==<br />
10% Research HBM and DRAM technology<br />
40% Simulation of the HBM, characterization, and model-building<br />
20% Implementation of the model in SV <br />
30% Evaluation <br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Improving_SystemVerilog_Support_for_Free_And_Open-Source_EDA_Tools_(1-3S/B)&diff=9833Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)2023-11-03T07:38:28Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Paulsc]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
<br />
* Type: Semester or Bachelor Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
Recently, a wide range of free and open-source electronic design automation (EDA) tools are emerging. Whilst being highly diverse in terms of application, they all share a common weakness; these tools only feature very limited SystemVerilog (SV) support. <br />
<br />
Our digital designs at IIS are written using the entire subset of synthesizable SystemVerilog code rendering most of our projects (PULP, Snitch, Ariane, ...) incompatible with most EDA tools. <br />
<br />
One solution to fix this issue would be a step-by-step simplification of the constructs that are not supported by the target EDA tool. <br />
<br />
The [https://github.com/MikePopoloski/slang slang] project is a lightweight SystemVerilog parser written in C++ with the best SV support within the open-source domain see [https://chipsalliance.github.io/sv-tests-results/ SV-Test Leaderboard]. Slang can parse SV, preprocess macros and includes, propagate constant parameters, uniquify the instances, and perform basic elaboration on the sourcecode. As a result, it produces an abstract syntax tree (AST) representation of the SV code as a JSON file. The simplification passes can then be done on the AST facilitating both their implementation and the check for correctness of the pass. Once transformed, slang can read the AST and reemit simpler SV code.<br />
<br />
== Project ==<br />
<br />
In this project, you will try to synthesize a Linux-capable SoC built around [https://github.com/openhwgroup/cva6 Ariane (CVA6)] using [https://github.com/YosysHQ/yosys Yosys]. To allow Yosys to read the sourcecode of Ariane, you will use slang to stepwise simplify the SV code as outlined above. <br />
<br />
== Character ==<br />
<br />
* 20% analysis of slang<br />
* 30% analysis of the SV support of Yosys and the Ariane sourcecode: Which constructs cannot be understood by Yosys<br />
* 50% implement and verify the simplification passes of the SV code<br />
<br />
== Prerequisites ==<br />
<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Knowledge of C++ and Python<br />
* Preferred: Experience with frontend compiler design and/or ASTs<br />
* Preferred: Experience with FOSS EDA tools</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Towards_a_High-performance_Open-source_Verification_Suite_for_AXI-based_Systems_(M/1-3S/B)&diff=9832Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)2023-11-03T07:38:12Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Towards a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester / Master Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
Almost all systems developed at IIS are using AXI (Advanced eXtensible Interface) as their main on-chip interface. So far we have relied on an extensive AXI verification infrastructure based on behavioral SystemVerilog code. With the advent of large high-performance scientific computing and machine-learning systems (Occamy, Mempool) simulation time increased massively making it in many cases even impossible to run the required simulations.<br />
<br />
Verilator is a fully open-source simulation environment allowing synthesizable SystemVerilog code to be translated into natively machine-executable code. This allows verilated designs to be simulated at speeds comparable to FPGAs.<br />
<br />
= Project =<br />
You will develop a set of testbench IPs to simulate AXI-based systems and IPs using Verilator. This includes:<br />
* An AXI manager unit to drive a bus using an API and/or file-based stimuli<br />
* An AXI subordinate device using real memory<br />
* A randomized version of the above IPs.<br />
<br />
You will have the chance to benchmark, optimize, and improve your testbenches simulating a large manycore system running real machine learning workloads (or booting Linux!).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Planning and design of the test environment<br />
* 40% Implementing a C++ testbench <br />
* 20% Verification of / Improving the testbench<br />
* 20% Benchmark and optimize the simulation speed of a large manycore system.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Knowledge of C/C++<br />
* Preferred: Knowledge of AXI4<br />
* Preferred: Experience with Verilator<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Enhancing_Our_DMA_Engine_With_Virtual_Memory_(M/1-3S/B)&diff=9831Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)2023-11-03T07:36:56Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines called iDMA. So far our DMA engine works on physical memory only, requiring either the processor to do the PM/VM translation or relying on an external IOMMU (IO Memory Management Unit).<br />
<br />
We have developed a minimal hardware PTW (page table walker) compliant with the RISC-V specification and we have already started to integrate it into the iDMA architecture. <br />
<br />
= Project =<br />
In this project, you will finish the integration of the PTW into the iDMA in the form of a modular midend. There are still multiple challenges to solve in the process (huge pages, PTW manager interface integration, programming model, error handling, ...).<br />
After completing the hardware, the unit has to be verified and fully characterized (performance, hardware overhead, power, ...).<br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the RISC-V spec, our PTW, and the iDMA<br />
* 30% Design and implementation of the VM midend<br />
* 20% Driver implementation, benchmarking<br />
* 30% Verification and evaluation OOC and in-system<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Extending_Our_DMA_Architecture_with_SiFives_TileLink_Protocol_(1-3S/B)&diff=9830Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)2023-11-03T07:36:35Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices introduced by SiFive. At IIS, we are developing a modular DMA architecture based on ARM's AXI (Advanced eXtensible Interface) protocol. We would now like to extend our DMA to be compatible with the TileLink protocol.<br />
<br />
<br />
= Project =<br />
You will extend our DMA with the TileLink protocol.<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the TileLink protocol, understanding the DMA architecture<br />
* 40% Design, implementation, and verification of the protocol layer<br />
* 40% Evaluation and optimization of your implementation<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Finalizing_and_Releasing_Our_Open-source_AXI4_IPs_(1-3S/B/2-3G)&diff=9829Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)2023-11-03T07:36:17Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester / Group Thesis <br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are developing THE free and open-source AXI4 (Advanced eXtensible Interface) IP suite (https://github.com/pulp-platform/axi). Our implementation is now almost at the point of reaching maturity. However, there are still some crucial key items missing before we can release our suite:<br />
* We lack core IPs (e.g. AXI Lite Data Width converter, the AXI4 reorder buffer (ROB), ...)<br />
* Protocol checkers (using SystemVerilog Assertions and Assume statements) are missing<br />
* We need a fully open-source CI (synthesis using Yosys, implementation using OpenRoad, simulation using Verilator/iverilog)<br />
* The IPs and the repository need to be homogenized (parameter names, interfaces, ...)<br />
<br />
= Project =<br />
In this project, you have the rare opportunity to go all in with AXI4-based interconnect IPs. You will develop and verify important AXI-based IPs, create an open-source fully-turnkey ASIC implementation flow to track non-functional figures of merit in CI, and you will have the chance to contribute to a project that is used all over the world in a multitude of designs.<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the AXI4 spec, look at our IPs, and get familiar with our design philosophy<br />
* 30% Create and verify missing IPs, verify existing IPs with missing test benches, and improve coverage and speed of existing TBs<br />
* 20% Create a fully open-source CI<br />
* 30% Homogenoze all IPs<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Extension_and_Evaluation_of_TinyDMA_(1-2S/B/2-3G)&diff=9828Extension and Evaluation of TinyDMA (1-2S/B/2-3G)2023-11-03T07:35:50Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Michaero]]<br />
[[Category:Paulsc]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing an architectural family of lightweight yet high-performance data movement engines. We call the configuration with the lowest area footprint TinyDMA.<br />
<br />
Currently, TinyDMA is based on the AMBA AXI4[1] on-chip communication standard. Next to AXI4, simpler protocols are used to transfer data around the chip. We employ widely in our SoCs three of these protocols: AXI 4 Lite, TCDM, and Regbus. Switching to such a (or multiple) simpler protocol(s) will reduce the area of TinyDMA further.<br />
<br />
TinyDMA only features the bare minimum hardware required to transport data over an AXI4 interconnect. This simplicity comes at a price: the legalization of the AXI transfers must be done in software.<br />
<br />
= Project =<br />
<br />
In this project, you extend TinyDMA to feature at least one simple protocol (e.g. AXI4 Lite) next to the already existing support for AXI4. You will evaluate the consequences of this switch in terms of area/speed/power (in a highly advanced 12nm node) as well as the impact on key performance numbers (latency, throughput, ...).<br />
<br />
<br />
== Character ==<br />
<br />
* 40% RTL Design and Verification<br />
* 20% Software / Driver / HAL writing (C)<br />
* 40% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge or experience with AXI and RISC-V<br />
<br />
= References =<br />
<br />
[1] https://github.com/pulp-platform/axi</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_Scalable_High-Performance_and_Low-Power_Interface_Based_on_the_I3C_Protocol_(1-3S/B)&diff=9827Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)2023-11-03T07:34:59Z<p>Tbenz: Created page with "<!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --> Category:Digital Category:High Performance SoCs Category:Comp..."</p>
<hr />
<div><!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Agarofalo]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
= Overview =<br />
<br />
This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance.<br />
<br />
== Status: Available ==<br />
<br />
* Type: Master's Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Project Description and Objectives =<br />
<br />
As smart phones, wearables, IoT (Internet of Things) devices, systems in automobiles and server environments become more advanced and complex, the necessity for more streamlined, high performance, scalable and cost-effective communication interfaces are required to control and transmit data with high speeds, in energy-saving and space-saving designs.<br />
<br />
I2C and SPI have long been the primary interface choice for embedded devices. While these interfaces are relatively simple to implement and have been widely adopted over the years, they both lack some critical features and have limitations. This applies especially for deeply-embedded applications, which can significantly impact designing densely packed systems.<br />
<br />
I3C (Improved-Inter Integrated Circuit) aims both to fix the limitations of legacy interfaces (I2C and SPI) and to also add other enhancements. I3C specification developed by MIPI Alliance [1] , is an intelligent multi-featured interface that improves upon the key attributes of traditional I2C and SPI interfaces to provide a new, unified, and high-performing solution. I3C is a serial communication interface implemented using a complementary metal oxide semiconductor (CMOS) I/O, which uses a two-wire interface to minimize pin counts and number of signal paths between components. It enables the use of higher bandwidth operating modes at very low power levels and allows simpler, yet more flexible design implementation. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus, but still supports the ability to switch to a higher data rate for communication at higher<br />
speeds between compliant I3C devices.<br />
<br />
This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance. The functionality of the peripheral will be tested through a set of custom test-benches, (following the UVM methodology [4] if the student is interested in this topic). Eventually, the project can be completed with the integration of the designed peripheral into a full SoC system that runs Linux [2]. To this extent, system-level integration, verification and evaluation must be performed as well as the design of the Linux drivers for the I3C peripheral.<br />
<br />
= Technical Activities =<br />
<br />
To achieve the project's goals, the student is required to complete the following activities:<br />
<br />
* Study and Analysis of the I3C communication protocol;<br />
* Design and implementation of the I3C I/O peripheral;<br />
* Design of test-benches for functional verification (possibly using UVM structure);<br />
* (Advanced, optional) Integration of the IP within a Linux-capable full SoC system;<br />
* (Very advanced, optional) Design and Integration of I3C drivers within the Linux kernels;<br />
<br />
= Weekly Reports =<br />
<br />
The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.<br />
<br />
= Learning Opportunities =<br />
<br />
The student will gain advanced knowledge on I/O SoC communication from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.<br />
<br />
== Character ==<br />
<br />
* 10% State-of-the-art review<br />
* (45-) 55% Hardware Design<br />
* 20% Functional Testing<br />
* (5-) 10% Evaluation and Documentation<br />
* 5% Final Report<br />
* (Optional, very advanced) 10% Firmware Design<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in deepening system I/O communication topics <br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Good knowledge of C and Assembly<br />
* Experience with Unix commands<br />
* Preferred: Experience with bash scripting<br />
* Preferred (not strictly required): Knowledge of the AXI4 protocol<br />
<br />
<br />
= References =<br />
<br />
[1] MIPI Alliance Specification for I3C® (Improved Inter Integrated Circuit), version 1.1.1, MIPI Alliance, Inc., 11 June 2021.<br />
<br />
[2] Ariane, RISC-V application processor: https://ieeexplore.ieee.org/abstract/document/8777130<br />
<br />
[3] MIPI Alliance “Introduction to the MIPI I3C Standardized Sensor Interface”, August 2016<br />
<br />
[4] https://learnuvmverification.com/</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_Scalable_High-Performance_and_Low-Power_Interface_Based_on_the_I3C_Protocol_(B/1-3S)&diff=9826Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)2023-11-03T07:34:48Z<p>Tbenz: Blanked the page</p>
<hr />
<div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_Scalable_High-Performance_and_Low-Power_Interface_Based_on_the_I3C_Protocol_(B/1-3S)&diff=9825Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)2023-11-03T07:30:52Z<p>Tbenz: Created page with "<!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --> Category:Digital Category:High Performance SoCs Category:Comp..."</p>
<hr />
<div><!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Agarofalo]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
= Overview =<br />
<br />
This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance.<br />
<br />
== Status: Available ==<br />
<br />
* Type: Master's Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Project Description and Objectives =<br />
<br />
As smart phones, wearables, IoT (Internet of Things) devices, systems in automobiles and server environments become more advanced and complex, the necessity for more streamlined, high performance, scalable and cost-effective communication interfaces are required to control and transmit data with high speeds, in energy-saving and space-saving designs.<br />
<br />
I2C and SPI have long been the primary interface choice for embedded devices. While these interfaces are relatively simple to implement and have been widely adopted over the years, they both lack some critical features and have limitations. This applies especially for deeply-embedded applications, which can significantly impact designing densely packed systems.<br />
<br />
I3C (Improved-Inter Integrated Circuit) aims both to fix the limitations of legacy interfaces (I2C and SPI) and to also add other enhancements. I3C specification developed by MIPI Alliance [1] , is an intelligent multi-featured interface that improves upon the key attributes of traditional I2C and SPI interfaces to provide a new, unified, and high-performing solution. I3C is a serial communication interface implemented using a complementary metal oxide semiconductor (CMOS) I/O, which uses a two-wire interface to minimize pin counts and number of signal paths between components. It enables the use of higher bandwidth operating modes at very low power levels and allows simpler, yet more flexible design implementation. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus, but still supports the ability to switch to a higher data rate for communication at higher<br />
speeds between compliant I3C devices.<br />
<br />
This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance. The functionality of the peripheral will be tested through a set of custom test-benches, (following the UVM methodology [4] if the student is interested in this topic). Eventually, the project can be completed with the integration of the designed peripheral into a full SoC system that runs Linux [2]. To this extent, system-level integration, verification and evaluation must be performed as well as the design of the Linux drivers for the I3C peripheral.<br />
<br />
= Technical Activities =<br />
<br />
To achieve the project's goals, the student is required to complete the following activities:<br />
<br />
* Study and Analysis of the I3C communication protocol;<br />
* Design and implementation of the I3C I/O peripheral;<br />
* Design of test-benches for functional verification (possibly using UVM structure);<br />
* (Advanced, optional) Integration of the IP within a Linux-capable full SoC system;<br />
* (Very advanced, optional) Design and Integration of I3C drivers within the Linux kernels;<br />
<br />
= Weekly Reports =<br />
<br />
The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.<br />
<br />
= Learning Opportunities =<br />
<br />
The student will gain advanced knowledge on I/O SoC communication from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.<br />
<br />
== Character ==<br />
<br />
* 10% State-of-the-art review<br />
* (45-) 55% Hardware Design<br />
* 20% Functional Testing<br />
* (5-) 10% Evaluation and Documentation<br />
* 5% Final Report<br />
* (Optional, very advanced) 10% Firmware Design<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in deepening system I/O communication topics <br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Good knowledge of C and Assembly<br />
* Experience with Unix commands<br />
* Preferred: Experience with bash scripting<br />
* Preferred (not strictly required): Knowledge of the AXI4 protocol<br />
<br />
<br />
= References =<br />
<br />
[1] MIPI Alliance Specification for I3C® (Improved Inter Integrated Circuit), version 1.1.1, MIPI Alliance, Inc., 11 June 2021.<br />
<br />
[2] Ariane, RISC-V application processor: https://ieeexplore.ieee.org/abstract/document/8777130<br />
<br />
[3] MIPI Alliance “Introduction to the MIPI I3C Standardized Sensor Interface”, August 2016<br />
<br />
[4] https://learnuvmverification.com/</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_Scalable_High-Performance_and_Low-Power_Interface_Based_on_the_I3C_Protocol_(1M)&diff=9824Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)2023-11-03T07:30:28Z<p>Tbenz: Blanked the page</p>
<hr />
<div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_a_CAN_Interface_to_Enable_Reliable_Sensors-to-Processors_Communication_for_Automotive-oriented_Embedded_Applications_(1M)&diff=9823Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)2023-11-03T07:28:58Z<p>Tbenz: </p>
<hr />
<div><!-- Design of a CAN Interface to Enable Sensors-to-Processors Communication for Automotive-Oriented Embedded Applications (1M) --><br />
<br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Agarofalo]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
= Overview =<br />
<br />
This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.<br />
<br />
== Status: Available ==<br />
<br />
* Type: Master's Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Project Description and Objectives =<br />
<br />
Modern embedded systems that run real-time applications require reliable protocols to enable the communications between sensors, actuators, controllers and other nodes. The controller Area Network (CAN) bus is a robust serial bus communications protocol that meet these requirements and allows microcontrollers and devices to communicate with each other's applications without a host computer. Initially specified and developed by Bosch in the early 1980s, this protocol is widely used today in industrial automation and other areas of networked embedded control, with applications in diverse products such as combustion and electric vehicles, agriculture, aviation and navigation electronics, elevators, medical instruments, railways applications, 3d printers..<br />
<br />
The CAN bus is a message-based protocol, designed originally for multiplexing electrical wiring within automobiles to save on copper. For each device, the data in a frame is transmitted serially but in such a way that if more than one device transmits at the same time, the highest priority device can continue while the others back off. Frames are received by all devices, including by the transmitting device. More information can be found in [1].<br />
<br />
This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.<br />
<br />
= Technical Activities =<br />
<br />
To achieve the project's goals, the student is required to complete the following activities:<br />
<br />
* Study the CAN protocol and existing implementations;<br />
* Design the CAN interface IP in SystemVerilog;<br />
* Integrate the peripheral into a full SoC system;<br />
* Verify the functionality of the IP through custom test-benches and available Linux-drivers;<br />
<br />
= Weekly Reports =<br />
<br />
The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.<br />
<br />
= Learning Opportunities =<br />
<br />
The student will gain advanced knowledge on I/O SoC communication, from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.<br />
<br />
== Character ==<br />
<br />
* 20% Study state-of-the-art and existing implementations of the IP;<br />
* 40% Hardware design;<br />
* 15% Functional Verification;<br />
* 20% Evaluation and Documentation;<br />
* 5% Final Report.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in deepening system I/O communication topics <br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Good knowledge of C and Assembly<br />
* Experience with Unix commands<br />
* Preferred: Experience with bash scripting<br />
* Preferred (not strictly required): Knowledge of the AXI4 protocol<br />
<br />
<br />
= References =<br />
<br />
[1] CAN Bus: https://en.wikipedia.org/wiki/CAN_bus</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Design_of_an_Energy-Efficient_Ethernet_Interface_for_Linux-capable_Systems&diff=9822Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems2023-11-03T07:28:34Z<p>Tbenz: </p>
<hr />
<div><!-- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (1M) --><br />
<br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:Heterogeneous Acceleration Systems]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Hot]]<br />
[[Category:Agarofalo]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
= Overview =<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Type: Master's Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Project Description and Objectives =<br />
<br />
Ethernet is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN) [1]. It was commercially introduced in 1980 and first standardized in 1983 as IEEE 802.3 <br />
<br />
Throughout its history, Ethernet data transfer rates have been increased from the original 2.94 Mbit/s [2] to the latest 400 Gbit/s, with rates up to 1.6 Tbit/s under development. The Ethernet standards include several wiring and signalling variants of the OSI physical layer.<br />
<br />
Since its inception, Ethernet has enjoyed remarkable growth. Today, hundreds of millions of Ethernet switch ports ship every year. Initially intended to connect computers on local networks, Ethernet applications now range from global telecommunications and supercomputing to industrial automation and avionics, including embedded computing products that nowadays feature at least one Ethernet interface. Ethernet standards have been defined for a wide range of speeds and transmission media to meet the needs of these diverse applications. <br />
<br />
Systems communicating over Ethernet divide a stream of data into shorter pieces called frames. Each frame contains the source and destination addresses and error-checking data so that damaged frames can be detected and discarded; most often, higher-layer protocols trigger the retransmission of lost frames. <br />
<br />
This project aims to improve the design of an Ethernet interface from a performance, power and area perspective, to meet the speed, bandwidth and flexibility requirements of automotive, aerial and other embedded applications. Interested students might conclude the project by investigating the challenges and opportunities of using Ethernet in real-time systems for automotive-oriented applications [3].<br />
<br />
= Technical Activities =<br />
<br />
To achieve the project's goals, the student is required to complete the following activities:<br />
<br />
* Study the Ethernet protocol, existing implementations and verification environments;<br />
* Design the Ethernet peripheral;<br />
* Verify the functionality through;<br />
* Integrate the IP into a full SoC system through an AXI-based DMA controller;<br />
* Extend the Linux driver according to the HW modifications/improvements.<br />
<br />
<br />
= Weekly Reports =<br />
<br />
The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.<br />
<br />
= Learning Opportunities =<br />
<br />
The student will gain advanced knowledge on I/O SoC communication, from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.<br />
<br />
== Character ==<br />
<br />
* 10% Study state-of-the-art and existing HDL code<br />
* 40% Hardware design<br />
* 15% Functional testing<br />
* 20% Firmware design<br />
* 5% Evaluation and Documentation<br />
* 5% Final Report<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in deepening system I/O communication topics <br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Good knowledge of C and Assembly<br />
* Experience with Unix commands<br />
* Preferred: Experience with bash scripting<br />
* Preferred (not strictly required): Knowledge of the AXI4 protocol<br />
<br />
<br />
= References =<br />
<br />
[1] Ethernet1: https://www.sciencedirect.com/topics/computer-science/ethernet-protocol<br />
<br />
[2] Ethernet2: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6203907<br />
<br />
[3] Real-Time Ethernet: https://reader.elsevier.com/reader/sd/pii/S1383762121001028?token=59EAFD338177EE3A24A123D888F16DFBFECCB46DA9CDAECF66749E3B3C451CDE9BE5BF7832681CC97700AD32E95093AA&originRegion=eu-west-1&originCreation=20221121103138</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Fitting_Power_Consumption_of_an_IP-based_HLS_Approach_to_Real_Hardware_(1-3S)&diff=9821Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)2023-11-03T07:27:44Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Reserved ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
Creating large SoCs fully by hand is a tedious and error-prone process. At IIS, we have developed Solder, a python-based framework that allows us to construct and configure large SoCs from a catalog of our highly-optimized IPs. <br />
<br />
We are in the process of enhancing Solder to not only construct larger systems but also give the developer rapid feedback about key numbers of merit (performance, area, timing, power, ...) facilitating the design space exploration process. <br />
<br />
The power consumption of a system usually is the most difficult figure of merit to acquire, as it usually has to be measured on (or at least correlated to) real silicon. <br />
<br />
<br />
= Project =<br />
<br />
In this project:<br />
* you first identify a key set of parameterization options of a given IP that best reflects the influence of the parameters on power consumption.<br />
* you then create RTL instantiating this minimal set of parametrization options in a stimuli generation framework.<br />
* you create an ASIC from this hardware and tape it out.<br />
<br />
== Character ==<br />
<br />
* 20% Evaluation<br />
* 20% RTL creation<br />
* 60% ASIC creation<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems (as the IP will be a DMA unit)<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Following (or have completed in a previous semester) VLSI II<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Technology-independent_USB1.0_Host_Implementation_Targetting_ASICSs_(1-3S/B)&diff=9820Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)2023-11-03T07:27:16Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Cykoenig]]<br />
[[Category:In progress]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are moving towards Linux-capable SoCs taped ou on ASICs. A wide range of peripheral devices is almost a necessity when working with Linux-capable ASICs (e.g. Mouse, Keyboard, Sound, ...). <br />
Implementing a silicon-proven IP for each peripheral type is quite a burden and requires a lot of effort. A simple solution to this problem was introduced in 1996 with USB 1.0. <br />
<br />
= Project =<br />
You will implement a USB 1.0/1.1 host device implementable both on ASICs and FPGAs (the latter mainly for verification).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the USB protocol and investigate existing solutions<br />
* 40% Design, implementation, and verification of the controller<br />
* 40% Evaluation and optimization of your implementation on FPGAs / in the Cheshire SoC, creation of constraints.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Technology-independent_USB1.0_Host_Implementation_Targetting_ASICSs_(1-3S/B)&diff=9819Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)2023-11-03T07:25:46Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Cykoenig]]<br />
[[Category:In Progress]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are moving towards Linux-capable SoCs taped ou on ASICs. A wide range of peripheral devices is almost a necessity when working with Linux-capable ASICs (e.g. Mouse, Keyboard, Sound, ...). <br />
Implementing a silicon-proven IP for each peripheral type is quite a burden and requires a lot of effort. A simple solution to this problem was introduced in 1996 with USB 1.0. <br />
<br />
= Project =<br />
You will implement a USB 1.0/1.1 host device implementable both on ASICs and FPGAs (the latter mainly for verification).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the USB protocol and investigate existing solutions<br />
* 40% Design, implementation, and verification of the controller<br />
* 40% Evaluation and optimization of your implementation on FPGAs / in the Cheshire SoC, creation of constraints.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=High_Performance_SoCs&diff=9818High Performance SoCs2023-11-03T07:24:36Z<p>Tbenz: /* Who are we */</p>
<hr />
<div>==High-Performance Systems-on-Chip==<br />
<br />
[[File:Snitch-bd.png|thumb|350px|The ''Snitch'' cluster couples tiny RISC-V ''Snitch'' cores with performant double-precision FPUs to minimize the control-to-compute ratio; it uses hardware loop buffers and stream semantic registers to achieve almost full FPU utilization.]]<br />
[[File:Floorplan_baikonur.png|thumb|350px|''Baikonur'', a 22 nm chip integrating two application-grade RISC-V Ariane cores and 3 Snitch clusters with 8 cores each.]]<br />
[[File:Manticore_concept.png|thumb|350px|Concept art for ''Manticore'', a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.]]<br />
<br />
Today, a multitude of data-driven applications such as machine learning, scientific computing, and big data demand an ever-increasing amount of '''parallel floating-point performance''' from computing systems. Increasingly, such applications must scale across a wide range of applications and energy budgets, from supercomputers simulating next week's weather to your smartphone cameras correcting for low light conditions.<br />
<br />
This brings challenges on multiple fronts:<br />
<br />
* '''Energy Efficiency''' becomes a major concern: As logic density increases, supplying these systems with energy and managing their heat dissipation requires increasingly complex solutions.<br />
<br />
* '''Memory bandwidth and latency''' become a major bottleneck as the amount of processed data increases. Despite continuous advances, memory lags behind computing in scaling, and many data-driven problems today are memory-bound.<br />
<br />
* '''Parallelization and scaling''' bring challenges of their own: on-chip interconnects may introduce significant area and performance overheads as they grow, and both the data and instruction streams of cores may compete for valuable memory bandwidth and interfere in a destructive way.<br />
<br />
While all state-of-the-art high-performance computing systems are constrained by the above issues, they are also subject to a fundamental trade-off between efficiency and flexibility. This forms a design space which includes the following paradigms:<br />
<br />
* '''Accelerators''' are designed to do one thing very well: they are very energy efficient and performant and usually offer predetermined data movement. However, they are not or barely programmable, inflexible, and monolithic in their design.<br />
<br />
* '''Superscalar Out-of-Order CPUs''', on the other end, provide extreme flexibility, full programmability, and reasonable performance across various workloads. However, they require large area and energy overheads for a given performance, use memory inefficiently, and are often hard to scale well to manycore systems.<br />
<br />
* '''GPUs''' are parallel and data-oriented by design, yet still meaningfully programmable, aiming for a sweet-spot between scalability, efficiency, and programmability. However, are still subject to memory access challenges and often require manual memory management for decent performance.<br />
<br />
'''How can we further improve on these existing paradigms?''' Can we design decently efficient and performant, yet freely programmable systems with scalable, performant memory systems?<br />
<br />
If these questions sound intriguing to you, consider joining us for a project or thesis! You can find currently available projects and our contact information below.<br />
<br />
==Our Activities==<br />
<br />
We are primarily interested in '''architecture design and hardware implementation''' for high-performance systems. However, ensuring high performance requires us to consider the '''entire hardware-software stack''':<br />
<br />
* '''HPC Software''': Design and porting of high-performance applications, benchmarks, compiler tools, and operating systems (Linux) to our hardware.<br />
* '''Hardware-software codesign''': Design of performance-aware algorithms and kernels and hardware that can be efficiently programmed for use in processor-based systems.<br />
* '''Architecture''': RTL implementation of energy-efficient designs with an emphasis on high utilization and throughput, as well as on efficient interoperability with existing IPs.<br />
* '''SoC design and Implementation''': Design of full high-performance systems-on-chips; implementation and tapeout on modern silicon technologies such as TSMC's 65 nm and GlobalFoundries' 22 nm nodes.<br />
* '''IC testing and Board-Level design''': Testing of the returning chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.<br />
<br />
Our current interests include systems with '''low control-to-compute ratios''', high-performance '''on-chip interconnects''', and '''scalable many-core systems'''. However, we are always happy to explore new domains; if you have an interesting idea, contact us and we can discuss it in detail!<br />
<br />
==Who are we==<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Smazzola_face_1to1.png|frameless|left|96px]]<br />
|<br />
===[[:User:Smazzola | Sergio Mazzola]]===<br />
* '''e-mail''': [mailto:smazzola@iis.ee.ethz.ch smazzola@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 81 49<br />
* '''office''': ETZ J76.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Paulsc_face_1to1.png|frameless|left|96px]]<br />
|<br />
===[[:User:Paulsc | Paul Scheffler]]===<br />
* '''e-mail''': [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 09 15<br />
* '''office''': ETZ J85<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Tbenz_face_pulp_team.jpg|frameless|left|96px]]<br />
|<br />
===[[:User:Tbenz | Thomas Benz]]===<br />
* '''e-mail''': [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 05 18<br />
* '''office''': ETZ J85<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Nwistoff_face_pulp_team.JPG|frameless|left|96px]]<br />
|<br />
===[[:User:Nwistoff | Nils Wistoff]]===<br />
* '''e-mail''': [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 06 75<br />
* '''office''': ETZ J85<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:lbertaccini_photo.jpg|frameless|left|96px]]<br />
|<br />
===[[:User:Lbertaccini | Luca Bertaccini]]===<br />
* '''e-mail''': [mailto:lbertaccini@iis.ee.ethz.ch lbertaccini@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 55 58<br />
* '''office''': ETZ J78<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Mperotti_face_pulp_team.jpg|frameless|left|96px]]<br />
|<br />
===[[:User:Mperotti | Matteo Perotti]]===<br />
* '''e-mail''': [mailto:mperotti@iis.ee.ethz.ch mperotti@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 05 25<br />
* '''office''': OAT U21<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Sriedel_face_pulp_team.jpg|frameless|left|96px]]<br />
|<br />
<br />
===[[:User:Sriedel | Samuel Riedel]]===<br />
* '''e-mail''': [mailto:sriedel@iis.ee.ethz.ch sriedel@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 65 69<br />
* '''office''': ETZ J71.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Tim_Fischer.jpeg|frameless|left|96px]]<br />
|<br />
<br />
===[[:User:Fischeti| Tim Fischer]]===<br />
* '''e-mail''': [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 59 12<br />
* '''office''': ETZ J76.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Colluca picture.png|frameless|left|96px]]<br />
|<br />
<br />
===[[:User:Colluca| Luca Colagrande]]===<br />
* '''e-mail''': [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]<br />
* '''office''': OAT U21<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File: Mbertuletti_squaredpicture.png|frameless|left|96px]]<br />
|<br />
<br />
===[[:User:Mbertuletti| Marco Bertuletti]]===<br />
* '''e-mail''': [mailto:mbertuletti@iis.ee.ethz.ch mbertuletti@iis.ee.ethz.ch]<br />
* '''office''': ETZ J69.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File: Yichao_Photo.jpeg|frameless|left|96px]]<br />
|<br />
<br />
===[[:User:Yiczhang| Yichao Zhang]]===<br />
* '''e-mail''': [mailto:yiczhang@iis.ee.ethz.ch yiczhang@iis.ee.ethz.ch]<br />
* '''office''': ETZ J76.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File: Agarofalo_new.jpeg|frameless|left|96px]]<br />
|<br />
===[[:User:Agarofalo| Angelo Garofalo]]===<br />
* '''e-mail''': [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]<br />
* '''office''': ETZ J78<br />
|}<br />
<br />
<!--Retired members<br />
{|<br />
| style="padding: 10px" | [[File:Akurth_face_pulp_team.jpeg|frameless|left|96px]]<br />
|<br />
===[[:User:Akurth | Andreas Kurth]]===<br />
* '''e-mail''': [mailto:akurth@iis.ee.ethz.ch akurth@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 04 87<br />
* '''office''': ETZ J69.2<br />
|}<br />
<br />
{|<br />
| style="padding: 10px" | [[File:Zarubaf_face_pulp_team.jpg|frameless|left|96px]]<br />
|<br />
===[[:User:Zarubaf | Florian Zaruba]]===<br />
* '''e-mail''': [mailto:zarubaf@iis.ee.ethz.ch zarubaf@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 65 56<br />
* '''office''': ETZ J89<br />
|}<br />
{|<br />
| style="padding: 10px" | [[File:Fschuiki_face_pulp_team.jpg|frameless|left|96px]]<br />
|<br />
===[[:User:Fschuiki | Fabian Schuiki]]===<br />
* '''e-mail''': [mailto:fschuiki@iis.ee.ethz.ch fschuiki@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 67 89<br />
* '''office''': ETZ J89<br />
|}<br />
{|<br />
| style="padding: 10px" | [[File:Matheusd_face_1to1.png|frameless|left|96px]]<br />
|<br />
===[[:User:Matheusd | Matheus Cavalcante]]===<br />
* '''e-mail''': [mailto:matheusd@iis.ee.ethz.ch matheusd@iis.ee.ethz.ch]<br />
* '''phone''': +41 44 632 54 96<br />
* '''office''': ETZ J69.2<br />
|}<br />
--><br />
<br />
<!--<br />
Who are we<br />
What do we do<br />
Where to find us<br />
--><br />
<br />
==Projects==<br />
<br />
All projects are annotated with one or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). <br />
<br />
* '''M''': Master's thesis: ''26 weeks'' full-time (6 months) for ''one student only''<br />
* '''S''': Semester project: ''14 weeks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''<br />
* '''B''': Bachelor's thesis: ''14 weeks'' half-time (1 semester lecture period) for ''one student only''<br />
* '''G''': Group project: ''14 weeks'' part-time (1 semester lecture period) for ''2-3 students''<br />
<br />
Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.<br />
<br />
===Available Projects===<br />
<DynamicPageList><br />
category = Available<br />
category = Digital<br />
category = High Performance SoCs<br />
suppresserrors=true<br />
ordermethod=sortkey<br />
order=ascending<br />
</DynamicPageList><br />
<br />
===Projects In Progress===<br />
<DynamicPageList><br />
category = In progress<br />
category = Digital<br />
category = High Performance SoCs<br />
suppresserrors=false<br />
ordermethod=sortkey<br />
order=ascending<br />
</DynamicPageList><br />
===Completed Projects===<br />
<DynamicPageList><br />
category = Completed<br />
category = Digital<br />
category = High Performance SoCs<br />
suppresserrors=true<br />
</DynamicPageList><br />
===Reserved Projects===<br />
<DynamicPageList><br />
category = Reserved<br />
category = Digital<br />
category = High Performance SoCs<br />
suppresserrors=true<br />
ordermethod=sortkey<br />
order=ascending<br />
</DynamicPageList></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Boundry_Scan_Generator_(1-3S/B/2-3G)&diff=9533Creating A Boundry Scan Generator (1-3S/B/2-3G)2023-08-29T09:35:21Z<p>Tbenz: Created page with "<!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:Computer Architecture Catego..."</p>
<hr />
<div><!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
When testing more complex ASICs in intricate packages, the JTAG boundary scan becomes a valuable tool to debug connectivity issues. Unfortunately, we currently have no way to generate the simple hardware required to implement the boundary scan in an arbitrary ASIC.<br />
<br />
= Project =<br />
You will create a tool that generates and inserts the required hardware around an existing ASIC design. Your generator should also create a testbench and the patterns for our ASIC tester to facilitate both verification and the actual testing of your boundary hardware. <br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study JTAG standard<br />
* 40% Design, implementation, and verification of the generator<br />
* 40% Implement your boundary scan hardware in an existing ASIC (and retape it)<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Technology-independent_USB1.0_Host_Implementation_Targetting_ASICSs_(1-3S/B)&diff=9532Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)2023-08-29T09:29:25Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Cykoenig]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: ASIC Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are moving towards Linux-capable SoCs taped ou on ASICs. A wide range of peripheral devices is almost a necessity when working with Linux-capable ASICs (e.g. Mouse, Keyboard, Sound, ...). <br />
Implementing a silicon-proven IP for each peripheral type is quite a burden and requires a lot of effort. A simple solution to this problem was introduced in 1996 with USB 1.0. <br />
<br />
= Project =<br />
You will implement a USB 1.0/1.1 host device implementable both on ASICs and FPGAs (the latter mainly for verification).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the USB protocol and investigate existing solutions<br />
* 40% Design, implementation, and verification of the controller<br />
* 40% Evaluation and optimization of your implementation on FPGAs / in the Cheshire SoC, creation of constraints.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9531Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-08-29T09:26:38Z<p>Tbenz: </p>
<hr />
<div><!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g. transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (based on iDMA) which is instead using the cluster TCDM as its buffer. <br />
<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. You then finally evaluate your approach compared to accelerators using a dedicated internal buffer. <br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Category:2023&diff=9530Category:20232023-08-29T09:24:20Z<p>Tbenz: Created blank page</p>
<hr />
<div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Technology-independent_USB1.0_Host_Implementation_Targetting_ASICSs_(1-3S/B)&diff=9529Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)2023-08-29T09:24:06Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Cykoenig]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are moving towards Linux-capable SoCs taped ou on ASICs. A wide range of peripheral devices is almost a necessity when working with Linux-capable ASICs (e.g. Mouse, Keyboard, Sound, ...). <br />
Implementing a silicon-proven IP for each peripheral type is quite a burden and requires a lot of effort. A simple solution to this problem was introduced in 1996 with USB 1.0. <br />
<br />
= Project =<br />
You will implement a USB 1.0/1.1 host device implementable both on ASICs and FPGAs (the latter mainly for verification).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the USB protocol and investigate existing solutions<br />
* 40% Design, implementation, and verification of the controller<br />
* 40% Evaluation and optimization of your implementation on FPGAs / in the Cheshire SoC, creation of constraints.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Reshuffling_Mid-end_For_Reorganizing_Data_Inside_The_Compute_Cluster_(1-3S/B)&diff=9528Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)2023-08-29T08:35:53Z<p>Tbenz: Created page with "<!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer..."</p>
<hr />
<div><!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
At IIS we are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When implemented as this cluster-level engine, iDMA has fine-granular access to the cluster-internal tightly-coupled data memory (TCDM).<br />
<br />
Traditionally, when reorganizing data, e.g. transposing a matrix, an accelerator requires a huge internal buffer to read the data in a dense format, reshuffle it, and write it out again as a dense stream. This requires a dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (based on iDMA) which is instead using the cluster TCDM as its buffer. <br />
<br />
<br />
= Project =<br />
You first investigate common data reshuffling operations and define their reshuffling characteristics. You then implement these reshuffling operations in our iDMA engine. You implement the required changes to access the Snitch TCDM memory at a word granularity (or even sub-word) and enable its usage as a buffer. You then finally evaluate your approach compared to accelerators using a dedicated internal buffer. <br />
<br />
== Character ==<br />
<br />
* 20% Getting familiar with the iDMA, and Snitch, evaluating reshuffle operations<br />
* 30% Implementing the reshuffle operation in the iDMA<br />
* 30% Integrating your accelerator in Snitch<br />
* 20% Evaluation<br />
<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-dma"><br />
[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Evaluating_The_Use_of_Snitch_In_The_PsPIN_RISC-V_In-network_Accelerator_(M)&diff=9527Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)2023-08-29T08:15:09Z<p>Tbenz: /* References */</p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
The SPCL group is working on PsPIN [1], an implementation of the sPIN programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP cluster to perform the calculations. We would now investigate if package processing could further be accelerated if we are using the Snitch [4] infrastructure.<br />
<br />
<br />
= Project =<br />
In this project, you will update the PULP implementation of sPIN (PsPIN) to the newest version of the PULP cluster. You then integrate Snitch, creating SsPIN in te process. Finally, you will evaluate the advantages and disadvantages of either implementation on an FPGA.<br />
<br />
== Character ==<br />
<br />
* 20% Getting used to PsPIN and updating the PULP cluster to the most recent version<br />
* 40% Implementing Snitch, creating SsPIN<br />
* 40% Evaluating both versions, comparing them quantitatively<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-pspin"><br />
[1] “Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021..” https://ieeexplore.ieee.org/iel7/12/9821023/09522037.pdf<br />
</div><br />
<div id="ref-spin><br />
[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. "sPIN: High-performance streaming Processing in the Network." In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.<br />
</div><br />
<div id="ref-pulp"><br />
[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. "PULP: A parallel ultra-low power platform for next generation IoT applications." In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.<br />
</div><br />
<div id="ref-snitch"><br />
[4] F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.” 2020.<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Evaluating_The_Use_of_Snitch_In_The_PsPIN_RISC-V_In-network_Accelerator_(M)&diff=9526Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)2023-08-29T08:14:50Z<p>Tbenz: </p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
The SPCL group is working on PsPIN [1], an implementation of the sPIN programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP cluster to perform the calculations. We would now investigate if package processing could further be accelerated if we are using the Snitch [4] infrastructure.<br />
<br />
<br />
= Project =<br />
In this project, you will update the PULP implementation of sPIN (PsPIN) to the newest version of the PULP cluster. You then integrate Snitch, creating SsPIN in te process. Finally, you will evaluate the advantages and disadvantages of either implementation on an FPGA.<br />
<br />
== Character ==<br />
<br />
* 20% Getting used to PsPIN and updating the PULP cluster to the most recent version<br />
* 40% Implementing Snitch, creating SsPIN<br />
* 40% Evaluating both versions, comparing them quantitatively<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-pspin"><br />
[1] “Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021..” https://ieeexplore.ieee.org/iel7/12/9821023/09522037.pdf<br />
</div><br />
<div id="ref-spin><br />
[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. "sPIN: High-performance streaming Processing in the Network." In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.<br />
</div><br />
<div id="ref-pulp"><br />
[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. "PULP: A parallel ultra-low power platform for next generation IoT applications." In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.<br />
</div><br />
</div><br />
<div id="ref-snitch"><br />
[4] F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.” 2020.<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Evaluating_The_Use_of_Snitch_In_The_PsPIN_RISC-V_In-network_Accelerator_(M)&diff=9525Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)2023-08-29T08:14:41Z<p>Tbenz: Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:FPGA Category:2023 Category:Master Thesis Category:Tbenz ..."</p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2023]]<br />
[[Category:Master Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
The SPCL group is working on PsPIN [1], an implementation of the sPIN programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP cluster to perform the calculations. We would now investigate if package processing could further be accelerated if we are using the Snitch [4] infrastructure.<br />
<br />
<br />
= Project =<br />
In this project, you will update the PULP implementation of sPIN (PsPIN) to the newest version of the PULP cluster. You then integrate Snitch, creating SsPIN in te process. Finally, you will evaluate the advantages and disadvantages of either implementation on an FPGA.<br />
<br />
== Character ==<br />
<br />
* 20% Getting used to PsPIN and updating the PULP cluster to the most recent version<br />
* 40% Implementing Snitch, creating SsPIN<br />
* 40% Evaluating both versions, comparing them quantitatively<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
<br />
= References =<br />
<br />
<div id="refs" class="references"><br />
<div id="ref-pspin"><br />
[1] “Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021..” https://ieeexplore.ieee.org/iel7/12/9821023/09522037.pdf<br />
</div><br />
<div id="ref-spin><br />
[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. "sPIN: High-performance streaming Processing in the Network." In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.<br />
</div><br />
<div id="ref-pulp"><br />
[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. "PULP: A parallel ultra-low power platform for next generation IoT applications." In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.<br />
</div><br />
</div><br />
<div id="ref-snitch"><br />
[4] F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.” 2020.<br />
</div><br />
</div></div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_A_Technology-independent_USB1.0_Host_Implementation_Targetting_ASICSs_(1-3S/B)&diff=9524Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)2023-08-29T07:46:38Z<p>Tbenz: Created page with "<!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C..."</p>
<hr />
<div><!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2023]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Cykoenig]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are moving towards Linux-capable SoCs taped ou on ASICs. A wide range of peripheral devices is almost a necessity when working with Linux-capable ASICs (e.g. Mouse, Keyboard, Sound, ...). <br />
Implementing a silicon-proven IP for each peripheral type is quite a burden and requires a lot of effort. A simple solution to this problem was introduced in 1996 with USB 1.0. <br />
<br />
= Project =<br />
You will implement a USB 1.0/1.1 host device implementable both on ASICs and FPGAs (the latter mainly for verification).<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the USB protocol and investigate existing solutions<br />
* 40% Design, implementation, and verification of the controller<br />
* 40% Evaluation and optimization of your implementation on FPGAs / in the Cheshire SoC, creation of constraints.<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Visited VLSI II or an equivalent lecture<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_a_Compact_Power_Supply_and_Monitoring_System_for_the_Occamy_Chip_(1-3S/B/2-3G)&diff=9523Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)2023-08-29T07:31:59Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Completed]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
We recently taped-out Occamy, (http://asic.ethz.ch/2022/Occamy.html, http://asic.ethz.ch/2022/Hedwig.html), a large-scale manycore chip featuring more than 400 cores. Occamy has a massive power consumption of over 100W (>130A at 0.8V) distributed over 11 power domains. <br />
Supplying the required power lets us face multiple challenges:<br />
* We have to supply over 130A of current at very low voltages<br />
* We have 11 independent supplies<br />
* The supplies need to be turned on in a given sequence<br />
* We want to monitor every supply closely<br />
<br />
= Project =<br />
In this project, you will design and create a power supply PCB for Occamy. It will feature 11 power supplies controlled and monitored using I2C. The board should contain a facility to safely control and bring up the supplies in the proper sequence (uController or FPGA).<br />
<br />
== Character ==<br />
<br />
* 30% Design of the Power Supply board<br />
* 30% Solder and test the board, program the device controlling the power-up sequence<br />
* 40% Characterize your supply, improve the design if required and create a second version.<br />
<br />
== Prerequisites ==<br />
<br />
* Preferred: PCB design and soldering experience<br />
* Preferred: Prior knowledge of FPGAs or uControllers<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=A_Flexible_FPGA-Based_Peripheral_Platform_Extending_Linux-Capable_Systems_on_Chip_(1-3S/B)&diff=9522A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)2023-08-29T07:31:45Z<p>Tbenz: </p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Nwistoff]]<br />
[[Category:Completed]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
<br />
Recent PULP chips, such as [http://asic.ethz.ch/2022/Occamy.html Occamy] or [http://asic.ethz.ch/2022/Neo.html Neo], feature a Linux-capable '''CVA6''' core [1] and a '''Serial Link''' off-chip interface. While the chips contain a few basic peripherals that allow running Linux (such as UART, GPIO), further peripherals to extend their functionality (e.g. Ethernet, USB Host, DVI/HDMI) are desirable.<br />
<br />
The idea of this project is to bring up an FPGA-based peripheral platform that can be connected to existing chips via Serial Link to extend their functionality.<br />
<br />
== Project ==<br />
<br />
This project involves both creating the FPGA platform and extending the software stack (e.g. Linux) running on the ASIC to use it.<br />
<br />
===== Tasks =====<br />
<br />
====== Hardware Design ====== <br />
<br />
* '''Serial-Link-capable base platform:''' Design an FPGA platform that can be accessed via Serial Link.<br />
<br />
* '''Integration of an Ethernet Peripheral:''' Integrate an Ethernet controller that communicates with the on-board Ethernet PHY.<br />
<br />
* '''Integration of PAPER:''' Integrate PAPER, a DVI/HDMI peripheral developed in previous student projects.<br />
<br />
====== Software Design ======<br />
<br />
* '''Bare-Metal Applications:''' Prototype bare-metal applications that access the integrated peripherals.<br />
<br />
* '''U-Boot and Linux Device Drivers:''' Integrate the necessary drivers in U-Boot and Linux to use the integrated peripherals<br />
<br />
<br />
====== Stretch Goals ======<br />
<br />
Depending on your progress and interests, several further steps can be considered, such as:<br />
<br />
* '''Integration of further peripherals:''' Further peripherals can be integrated in hardware and software, such as SPI devices and a USB Host.<br />
<br />
We can also discuss targeting a subset of the tasks above depending on your time frame and interests.<br />
<br />
===== Requirements ===== <br />
<br />
* Strong interest system design and hardware/software interaction<br />
* Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I<br />
* Basic knowledge of operating systems<br />
<br />
Composition: 40% RTL Implementation, 20% Verification, 40% Software Design<br />
<br />
===== Project Supervisors ===== <br />
* [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
* [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
* [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch]<br />
<br />
== References ==<br />
<br />
* [1] https://github.com/openhwgroup/cva6</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Fitting_Power_Consumption_of_an_IP-based_HLS_Approach_to_Real_Hardware_(1-3S)&diff=9521Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)2023-08-29T07:31:18Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Paulsc]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Reserved ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
Creating large SoCs fully by hand is a tedious and error-prone process. At IIS, we have developed Solder, a python-based framework that allows us to construct and configure large SoCs from a catalog of our highly-optimized IPs. <br />
<br />
We are in the process of enhancing Solder to not only construct larger systems but also give the developer rapid feedback about key numbers of merit (performance, area, timing, power, ...) facilitating the design space exploration process. <br />
<br />
The power consumption of a system usually is the most difficult figure of merit to acquire, as it usually has to be measured on (or at least correlated to) real silicon. <br />
<br />
<br />
= Project =<br />
<br />
In this project:<br />
* you first identify a key set of parameterization options of a given IP that best reflects the influence of the parameters on power consumption.<br />
* you then create RTL instantiating this minimal set of parametrization options in a stimuli generation framework.<br />
* you create an ASIC from this hardware and tape it out.<br />
<br />
== Character ==<br />
<br />
* 20% Evaluation<br />
* 20% RTL creation<br />
* 60% ASIC creation<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems (as the IP will be a DMA unit)<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Following (or have completed in a previous semester) VLSI II<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=A_Flexible_FPGA-Based_Peripheral_Platform_Extending_Linux-Capable_Systems_on_Chip_(1-3S/B)&diff=8466A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)2023-01-05T07:49:00Z<p>Tbenz: </p>
<hr />
<div>[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:FPGA]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Nwistoff]]<br />
[[Category:Reserved]]<br />
<br />
<br />
== Status: Available ==<br />
<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
** [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
** [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch]<br />
<br />
== Introduction ==<br />
<br />
Recent PULP chips, such as [http://asic.ethz.ch/2022/Occamy.html Occamy] or [http://asic.ethz.ch/2022/Neo.html Neo], feature a Linux-capable '''CVA6''' core [1] and a '''Serial Link''' off-chip interface. While the chips contain a few basic peripherals that allow running Linux (such as UART, GPIO), further peripherals to extend their functionality (e.g. Ethernet, USB Host, DVI/HDMI) are desirable.<br />
<br />
The idea of this project is to bring up an FPGA-based peripheral platform that can be connected to existing chips via Serial Link to extend their functionality.<br />
<br />
== Project ==<br />
<br />
This project involves both creating the FPGA platform and extending the software stack (e.g. Linux) running on the ASIC to use it.<br />
<br />
===== Tasks =====<br />
<br />
====== Hardware Design ====== <br />
<br />
* '''Serial-Link-capable base platform:''' Design an FPGA platform that can be accessed via Serial Link.<br />
<br />
* '''Integration of an Ethernet Peripheral:''' Integrate an Ethernet controller that communicates with the on-board Ethernet PHY.<br />
<br />
* '''Integration of PAPER:''' Integrate PAPER, a DVI/HDMI peripheral developed in previous student projects.<br />
<br />
====== Software Design ======<br />
<br />
* '''Bare-Metal Applications:''' Prototype bare-metal applications that access the integrated peripherals.<br />
<br />
* '''U-Boot and Linux Device Drivers:''' Integrate the necessary drivers in U-Boot and Linux to use the integrated peripherals<br />
<br />
<br />
====== Stretch Goals ======<br />
<br />
Depending on your progress and interests, several further steps can be considered, such as:<br />
<br />
* '''Integration of further peripherals:''' Further peripherals can be integrated in hardware and software, such as SPI devices and a USB Host.<br />
<br />
We can also discuss targeting a subset of the tasks above depending on your time frame and interests.<br />
<br />
===== Requirements ===== <br />
<br />
* Strong interest system design and hardware/software interaction<br />
* Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I<br />
* Basic knowledge of operating systems<br />
<br />
Composition: 40% RTL Implementation, 20% Verification, 40% Software Design<br />
<br />
===== Project Supervisors ===== <br />
* [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
* [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]<br />
* [[:User:Cykoenig | Cyril Koenig]]: [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch]<br />
<br />
== References ==<br />
<br />
* [1] https://github.com/openhwgroup/cva6</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Creating_a_Compact_Power_Supply_and_Monitoring_System_for_the_Occamy_Chip_(1-3S/B/2-3G)&diff=8465Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)2023-01-05T07:48:26Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Reserved]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis or Group Project<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
<br />
We recently taped-out Occamy, (http://asic.ethz.ch/2022/Occamy.html, http://asic.ethz.ch/2022/Hedwig.html), a large-scale manycore chip featuring more than 400 cores. Occamy has a massive power consumption of over 100W (>130A at 0.8V) distributed over 11 power domains. <br />
Supplying the required power lets us face multiple challenges:<br />
* We have to supply over 130A of current at very low voltages<br />
* We have 11 independent supplies<br />
* The supplies need to be turned on in a given sequence<br />
* We want to monitor every supply closely<br />
<br />
= Project =<br />
In this project, you will design and create a power supply PCB for Occamy. It will feature 11 power supplies controlled and monitored using I2C. The board should contain a facility to safely control and bring up the supplies in the proper sequence (uController or FPGA).<br />
<br />
== Character ==<br />
<br />
* 30% Design of the Power Supply board<br />
* 30% Solder and test the board, program the device controlling the power-up sequence<br />
* 40% Characterize your supply, improve the design if required and create a second version.<br />
<br />
== Prerequisites ==<br />
<br />
* Preferred: PCB design and soldering experience<br />
* Preferred: Prior knowledge of FPGAs or uControllers<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Finalizing_and_Releasing_Our_Open-source_AXI4_IPs_(1-3S/B/2-3G)&diff=8321Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)2022-11-08T06:07:30Z<p>Tbenz: Created page with "<!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture [..."</p>
<hr />
<div><!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Group Project]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester / Group Thesis <br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
At IIS we are developing THE free and open-source AXI4 (Advanced eXtensible Interface) IP suite (https://github.com/pulp-platform/axi). Our implementation is now almost at the point of reaching maturity. However, there are still some crucial key items missing before we can release our suite:<br />
* We lack core IPs (e.g. AXI Lite Data Width converter, the AXI4 reorder buffer (ROB), ...)<br />
* Protocol checkers (using SystemVerilog Assertions and Assume statements) are missing<br />
* We need a fully open-source CI (synthesis using Yosys, implementation using OpenRoad, simulation using Verilator/iverilog)<br />
* The IPs and the repository need to be homogenized (parameter names, interfaces, ...)<br />
<br />
= Project =<br />
In this project, you have the rare opportunity to go all in with AXI4-based interconnect IPs. You will develop and verify important AXI-based IPs, create an open-source fully-turnkey ASIC implementation flow to track non-functional figures of merit in CI, and you will have the chance to contribute to a project that is used all over the world in a multitude of designs.<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the AXI4 spec, look at our IPs, and get familiar with our design philosophy<br />
* 30% Create and verify missing IPs, verify existing IPs with missing test benches, and improve coverage and speed of existing TBs<br />
* 20% Create a fully open-source CI<br />
* 30% Homogenoze all IPs<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Extending_Our_DMA_Architecture_with_SiFives_TileLink_Protocol_(1-3S/B)&diff=8320Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)2022-11-08T05:52:11Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices introduced by SiFive. At IIS, we are developing a modular DMA architecture based on ARM's AXI (Advanced eXtensible Interface) protocol. We would now like to extend our DMA to be compatible with the TileLink protocol.<br />
<br />
<br />
= Project =<br />
You will extend our DMA with the TileLink protocol.<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the TileLink protocol, understanding the DMA architecture<br />
* 40% Design, implementation, and verification of the protocol layer<br />
* 40% Evaluation and optimization of your implementation<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenzhttp://iis-projects.ee.ethz.ch/index.php?title=Extending_Our_DMA_Architecture_with_SiFives_TileLink_Protocol_(1-3S/B)&diff=8319Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)2022-11-08T05:51:49Z<p>Tbenz: </p>
<hr />
<div><!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --><br />
<br />
[[Category:Digital]]<br />
[[Category:High Performance SoCs]]<br />
[[Category:Computer Architecture]]<br />
[[Category:2022]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Bachelor Thesis]]<br />
[[Category:Tbenz]]<br />
[[Category:Available]]<br />
<br />
<br />
= Overview =<br />
<br />
== Status: Available ==<br />
<br />
* Type: Bachelor / Semester Thesis<br />
* Professor: Prof. Dr. L. Benini<br />
* Supervisors:<br />
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
<br />
= Introduction =<br />
TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices introduced by SiFive. At IIS, we are developing a modular DMA architecture based on ARM's AXI (Advanced eXtensible Interface) protocol. We would now like to extend our DMA to be compatible with the TileLink protocol.<br />
<br />
<br />
= Project =<br />
Zou will extend our DMA with the TileLink protocol.<br />
<br />
<br />
== Character ==<br />
<br />
* 20% Study the TileLink protocol, understanding the DMA architecture<br />
* 40% Design, implementation, and verification of the protocol layer<br />
* 40% Evaluation and optimization of your implementation<br />
<br />
== Prerequisites ==<br />
<br />
* Interest in memory systems<br />
* Experience with digital design in SystemVerilog as taught in VLSI I<br />
* Preferred: Knowledge of AXI4<br />
<br />
= References =</div>Tbenz