http://iis-projects.ee.ethz.ch/api.php?action=feedcontributions&user=Tjang&feedformat=atom
iis-projects - User contributions [en]
2024-03-29T06:35:37Z
User contributions
MediaWiki 1.28.0
http://iis-projects.ee.ethz.ch/index.php?title=File:LowPowerAnalog2.png&diff=4170
File:LowPowerAnalog2.png
2018-09-19T09:49:21Z
<p>Tjang: </p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:LowPowerAnalog1.png&diff=4169
File:LowPowerAnalog1.png
2018-09-19T09:48:57Z
<p>Tjang: </p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4167
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-19T09:46:07Z
<p>Tjang: </p>
<hr />
<div>[[File:ApplicationSpecificPLL.png|thumb|600px]]<br />
==Short Description==<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
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GROUP<br />
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[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
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TYPE OF WORK<br />
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[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:ApplicationSpecificPLL.png&diff=4166
File:ApplicationSpecificPLL.png
2018-09-19T09:45:38Z
<p>Tjang: Tjang uploaded a new version of File:ApplicationSpecificPLL.png</p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:ApplicationSpecificPLL.png&diff=4165
File:ApplicationSpecificPLL.png
2018-09-19T09:45:07Z
<p>Tjang: </p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4164
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-19T09:44:53Z
<p>Tjang: </p>
<hr />
<div>[[File:ApplicationSpecificPLL.png|thumb|400px]]<br />
==Short Description==<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:NeuralRecording.png&diff=4163
File:NeuralRecording.png
2018-09-19T09:37:08Z
<p>Tjang: </p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4152
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-18T08:44:24Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4151
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-18T08:43:58Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
<br />
.res-img img {<br />
max-width:100%;<br />
height:auto;<br />
}<br />
<div class="res-img"><br />
[[File:AnalogDigitalPLL.png]]<br />
</div><br />
<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4150
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-18T08:41:15Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
[[File:AnalogDigitalPLL.png|responsive]]<br />
<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4149
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-18T08:38:53Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
[[File:AnalogDigitalPLL.png|packed]]<br />
<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4148
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-18T08:35:44Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
[[File:AnalogDigitalPLL.png]]<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:AnalogDigitalPLL.png&diff=4147
File:AnalogDigitalPLL.png
2018-09-18T08:32:38Z
<p>Tjang: Tjang uploaded a new version of File:AnalogDigitalPLL.png</p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=4143
Main Page
2018-09-17T10:35:08Z
<p>Tjang: /* Analog and Mixed Signal Interfaces Group(Prof. Jang) */</p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
In this page you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 4 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[AnalogInt| Analog and Mixed Signal Interfaces]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
<DynamicPageList><br />
category = Analog<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
===[[AnalogInt| Analog and Mixed Signal Interfaces Group (Prof. Jang)]]===<br />
<DynamicPageList><br />
category = AnalogInt<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[Computer Architecture]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous Acceleration Systems]]<br />
* [[Event-Driven Computing]]<br />
* [[Predictable Execution]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Transient Computing]]<br />
* [[RF SoCs for the Internet of Things]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Main_Page&diff=4142
Main Page
2018-09-17T10:34:36Z
<p>Tjang: /* Analog and Mixed Signal Interfaces Group(Prof. Taekwang Jang) */</p>
<hr />
<div>__NOTOC__<br />
<CENTER><H1> Welcome to IIS-Projects</H1></CENTER><br />
In this page you will find student and research projects at the [http://www.iis.ee.ethz.ch Integrated Systems Laboratory] of the [http://www.ethz.ch ETH Zurich].<br />
<br />
==Institute Organization==<br />
The IIS Consists of 4 main research groups<br />
* [[Analog| Analog and Mixed Signal Design]]<br />
* [[AnalogInt| Analog and Mixed Signal Interfaces]]<br />
* [[Digital| Digital Circuits and Systems]]<br />
* [[:Category:Nano-TCAD|Nano-TCAD]]<br />
<br />
===[[Analog|Analog and Mixed Signal Design Group (Prof. Huang)]]===<br />
<DynamicPageList><br />
category = Analog<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
===[[AnalogInt| Analog and Mixed Signal Interfaces Group(Prof. Jang)]]===<br />
<DynamicPageList><br />
category = AnalogInt<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
<br />
===[[Digital|Digital Circuits and Systems Group (Prof. Benini)]]===<br />
* [[Computer Architecture]]<br />
* [[Acceleration and Transprecision]]<br />
* [[Heterogeneous Acceleration Systems]]<br />
* [[Event-Driven Computing]]<br />
* [[Predictable Execution]]<br />
* [[Low Power Embedded Systems and Wireless Sensors Networks]]<br />
* [[Embedded Artificial Intelligence:Systems And Applications]]<br />
* [[Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets]]<br />
* [[Transient Computing]]<br />
* [[RF SoCs for the Internet of Things]]<br />
* [[Energy Efficient Autonomous UAVs]]<br />
* [[Biomedical System on Chips]]<br />
* [[Digital Medical Ultrasound Imaging]]<br />
* [[Cryptography|Cryptographic Hardware]]<br />
* [[Deep Learning Projects|Deep Learning Acceleration]]<br />
* [[Human Intranet]]<br />
<br />
===[[:Category:Nano-TCAD|Nano-TCAD Group (Prof. Luisier)]]===<br />
<DynamicPageList><br />
category = Nano-TCAD<br />
category = Available<br />
category = Hot<br />
</DynamicPageList><br />
===[[:Category:Collaboration|Collaborations with other groups/departments]]===<br />
<DynamicPageList><br />
category = Collaboration<br />
category = Available<br />
</DynamicPageList><br />
<br />
==Selected Projects in Progress==<br />
''For a complete list, see [[:Category:In progress|Projects in Progress]].''<br />
<DynamicPageList><br />
count = 5<br />
category = In progress<br />
</DynamicPageList><br />
<br />
==Selected Completed Projects==<br />
''For a complete list, see [[:Category:Completed|Completed Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Selected Research Projects==<br />
''For a complete list, see [[:Category:Research|Research Projects]].''<br />
<DynamicPageList><br />
count = 5<br />
category = Completed<br />
</DynamicPageList><br />
<br />
==Links to Other IIS Webpages==<br />
; [http://www.iis.ee.ethz.ch http://www.iis.ee.ethz.ch] <br />
: Integrated Systems Laboratory Main homepage<br />
; [http://www.nano-tcad.ethz.ch http://www.nano-tcad.ethz.ch] <br />
:Nano-TCAD group homepage<br />
; [http://www.dz.ee.ethz.ch http://www.dz.ee.ethz.ch]<br />
: Microelectronics Design Center<br />
; [http://asic.ethz.ch/cg http://asic.ethz.ch/cg]<br />
: The IIS-ASIC Chip Gallery<br />
; [http://eda.ee.ethz.ch http://eda.ee.ethz.ch]<br />
: EDA Wiki (''ETH Zurich internal access only!'')</div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=File:AnalogDigitalPLL.png&diff=4139
File:AnalogDigitalPLL.png
2018-09-17T10:30:56Z
<p>Tjang: </p>
<hr />
<div></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4138
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-17T10:24:20Z
<p>Tjang: /* Available Projects */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
: Ultra low noise frequency synthesizers for 5G LTE<br />
: Frequency synthesis for digital circuits<br />
: Spread spectrum PLLs<br />
: Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
<br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang
http://iis-projects.ee.ethz.ch/index.php?title=Application_Specific_Frequency_Synthesizers_(Analog/Digital_PLLs)&diff=4135
Application Specific Frequency Synthesizers (Analog/Digital PLLs)
2018-09-17T07:28:20Z
<p>Tjang: /* Short Description */</p>
<hr />
<div>[[File:AnalogDigitalPLL|thumb|400px]]<br />
==Short Description==<br />
Various aspects of a frequency synthesizers have been widely investigated for several decades, such as output phase noise, output frequency range, locking time, supply rejection, tolerance to variabilities, spur minimization and input noise rejection. Consequently, numerous innovations have been introduced for improving the performance such as sub-sampling PLL, Multiplying DLL, replica-biasing, DSM noise cancellation, digital-to-time converter based fractional-N synthesis, injection locking and so on. Therefore, a recent frequency synthesizer is highly well-optimized so that its performance is closed to the theoretical limits.<br />
In this project, students will learn the key techniques for an advanced frequency synthesizer by designing a frequency synthesizer specific to the application requirements.<br />
<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Semester or master students<br />
: Contact: Prof. Taekwang Jang <tjang@ethz.ch><br />
===Prerequisites===<br />
: Basic knowledge in analog circuit design<br />
===Available Projects ===<br />
Ultra low noise frequency synthesizers for 5G LTE<br />
Frequency synthesis for digital circuits<br />
Spread spectrum PLLs<br />
Inductor-less low noise frequency synthesizers<br />
<!-- <br />
===Status: In Progress ===<br />
: Student A, StudentB<br />
: Supervision: <br />
---><br />
===Character===<br />
<br />
: 30% Theory<br />
: 30% Simulation<br />
: 40% Circuit design<br />
<br />
<br />
===Professor===<br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] --><br />
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] ---><br />
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] ---><br />
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] ---><br />
Prof. Taekwang Jang <tjang@ethz.ch><br />
<br />
[[#top|↑ top]]<br />
<br />
==Links== <br />
[[Category:AnalogInt]]<br />
[[Category:Hot]]<br />
[[Category:Available]]<br />
[[Category:Master Thesis]]<br />
[[Category:Semester Thesis]]<br />
<br />
[[#top|↑ top]]<br />
<!-- <br />
<br />
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES<br />
<br />
GROUP<br />
[[Category:Digital]]<br />
[[Category:Analog]]<br />
[[Category:TCAD]]<br />
[[Category:Nano Electronic]]<br />
<br />
STATUS<br />
[[Category:Available]]<br />
[[Category:In progress]]<br />
[[Category:Completed]]<br />
<br />
TYPE OF WORK<br />
[[Category:Semester Thesis]]<br />
[[Category:Master Thesis]]<br />
[[Category:PhD Thesis]]<br />
[[Category:Research]]<br />
<br />
NAMES OF EU/CTI/NT PROJECTS<br />
[[Category:UltrasoundToGo]]<br />
[[Category:IcySoC]]<br />
[[Category:PSocrates]]<br />
[[Category:UlpSoC]]<br />
---></div>
Tjang