Design and Implementation of a Convolutional Neural Network Accelerator ASIC
From iis-projects
The printable version is no longer supported and may have rendering errors. Please update your browser bookmarks and please use the default browser print function instead.
Short Description
todo
Status: In Progress
- David Gschwend, Christoph Mayer, Samuel Willi
- Supervision: Lukas Cavigelli, Beat Muheim
- Date: Fall Semester 2014 (sem14h17, sem14h18, sem14h19)
Prerequisites
- Knowledge of Matlab
- Interest in video processing and VLSI design
- VLSI 1 and enrolment in VLSI 2 is required
- At least one student has to test the chip as part of the VLSI 3 lecture, if the ASIC should be manufactured.
Character
- 10% Theory / Literature Research
- 60% VLSI Architecture, Implementation & Verification
- 30% VLSI back-end Design
Professor
Detailed Task Description
Goals
- Explore various architectures to perform the 2D convolutions used in convolutional networks.
- Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing.
Practical Details
Results
Links