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- ...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an * programming the PULP processor for the specific application, otimize the code and carry out in-field testi4 KB (631 words) - 11:39, 21 July 2017
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp10 KB (1,357 words) - 16:25, 30 October 2020
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (351 words) - 16:19, 27 February 2018
- ...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream. *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]3 KB (394 words) - 16:19, 27 February 2018
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (440 words) - 16:15, 1 September 2017
- ...mic power controller algorithm is then needed to always configure the PULP processor in the most energy efficient point.3 KB (348 words) - 15:31, 13 September 2016
- ...ps (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking3 KB (389 words) - 11:20, 14 September 2016
- while the DBB processing can be done in a CPU, a Digital Signal Processor (DSP), an Appli- Open-RISC processor. The processor can be used to control the baseband blocks as well as to6 KB (900 words) - 16:58, 7 May 2018
- ...ystems Laboratory (IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-9 KB (1,427 words) - 18:36, 5 September 2019
- [[Category:Processor]]3 KB (392 words) - 14:17, 5 April 2022
- ...ger part of the affected digital baseband processing is mapped to a RISC-V processor, most of the work throughout the project requires embedded C coding, with s [[Category:Processor]]3 KB (462 words) - 13:54, 13 November 2020
- [[Category:Processor]]4 KB (467 words) - 13:38, 10 November 2020
- ...-power devices such as the PULP chips we develop at IIS. However, a vector processor shares many similarities with custom-designed HW accelerators that we have [[Category:Processor]]6 KB (916 words) - 15:50, 7 December 2018
- [[Category:Processor]]4 KB (546 words) - 11:33, 17 April 2020
- [[Category:Processor]]3 KB (372 words) - 20:22, 1 April 2019
- ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an [[Category:Processor]]3 KB (401 words) - 19:08, 29 January 2021
- ...it should not have any impact on the maximum achievable clock speed of the processor. Another challenge in designing a trace debugger is the fact that on-chip R * Basic knowledge of computer architecture/processor design as thought in the Energy-Efficient Parallel Computing Systems for Da5 KB (729 words) - 11:27, 11 December 2018
- [[Category:Processor]]3 KB (366 words) - 15:39, 10 November 2020
- architectures, where a powerful host processor is coupled to massively pushing for an architectural model where the host processor and the6 KB (865 words) - 12:16, 17 November 2017
- [[Category:Processor]]3 KB (409 words) - 13:58, 9 November 2017