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Reliable transmission of information despite unfavorable circumstances is the basis of digital communication. In order to provide good quality of service and high throughput powerful coding schemes are required in almost any application. Turbo codes offer outstanding error correction capabilities combined with efficient hardware architectures, which made them the method of choice in a great variety of applications ranging from 3G/4G cellular networks to satellite communications. Recently a new class of Turbo codes has been proposed, which can improve the error rate even further. Finding an efficient implementation for these 3D-Turbo codes will be your task during this thesis. You will start by evaluating the performance compared to the regular Turbo codes in MATLAB, then design a suitable architecture in order to arrive at a highly efficient VHDL implementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology.
 
Reliable transmission of information despite unfavorable circumstances is the basis of digital communication. In order to provide good quality of service and high throughput powerful coding schemes are required in almost any application. Turbo codes offer outstanding error correction capabilities combined with efficient hardware architectures, which made them the method of choice in a great variety of applications ranging from 3G/4G cellular networks to satellite communications. Recently a new class of Turbo codes has been proposed, which can improve the error rate even further. Finding an efficient implementation for these 3D-Turbo codes will be your task during this thesis. You will start by evaluating the performance compared to the regular Turbo codes in MATLAB, then design a suitable architecture in order to arrive at a highly efficient VHDL implementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology.
  
===Status: Available ===
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===Status: Completed ===
: Looking for 1-2 Semester/Master students
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<!--: Looking for 1-2 Semester/Master students
: Contact: [[:User:Belfanti Sandro Belfanti]]
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: Contact: [[:User:Belfanti | Sandro Belfanti]]
 
+
--->
 
===Prerequisites===
 
===Prerequisites===
 
: VLSI I
 
: VLSI I
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<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
==Detailed Task Description==
 
 
===Goals===
 
===Practical Details===
 
* '''[[Project Plan]]'''
 
* '''[[Project Meetings]]'''
 
* '''[[Design Review]]'''
 
* '''[[Coding Guidelines]]'''
 
* '''[[Final Report]]'''
 
* '''[[Final Presentation]]'''
 
 
==Results==
 
 
==Links==
 
 
[[#top|↑ top]]
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]
[[Category:Available]]
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[[Category:Completed]]
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
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[[Category:Master Thesis]]
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[[Category:Belfanti]]
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[[Category:ASIC]]
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[[Category:Telecommunications]]
  
 
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Latest revision as of 11:33, 15 April 2016

Creating 3D Turbo Codes.jpg

Short Description

A 3D turbo decoder layout of a previous project

Reliable transmission of information despite unfavorable circumstances is the basis of digital communication. In order to provide good quality of service and high throughput powerful coding schemes are required in almost any application. Turbo codes offer outstanding error correction capabilities combined with efficient hardware architectures, which made them the method of choice in a great variety of applications ranging from 3G/4G cellular networks to satellite communications. Recently a new class of Turbo codes has been proposed, which can improve the error rate even further. Finding an efficient implementation for these 3D-Turbo codes will be your task during this thesis. You will start by evaluating the performance compared to the regular Turbo codes in MATLAB, then design a suitable architecture in order to arrive at a highly efficient VHDL implementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology.

Status: Completed

Prerequisites

VLSI I
MATLAB and VHDL is an advantage

Character

30% Theory/Simulation
50% VHDL
20% ASIC Implementation

Professor

Qiuting Huang