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[[File:LTE Synchronization.png|thumb]]
 
[[File:LTE Synchronization.png|thumb]]
 
==Short Description==
 
==Short Description==
Wireless communication imposes immense challenges on receiver
+
Wireless communication imposes immense challenges on receiver design
design in case the transmitter and receiver are not synchronized.
+
in case the transmitter and receiver are not synchronized. Strongly
Strongly centralized network topologies such as cellular communication
+
centralized network topologies such as cellular communication networks
networks rely on high-quality hardware at the base transceiver station
+
rely on high-quality hardware at the base transceiver station
 
(BTS). This allows the network to be in sync with a common external
 
(BTS). This allows the network to be in sync with a common external
signal (such as GPS). On the Mobile Station (MS) side, however, it cannot
+
signal (such as GPS). On the Mobile Station (MS) side, however, it
be guaranteed that such an external common clock signal is available at
+
cannot be guaranteed that such an external common clock signal is
all times. Therefore, the BTS transmits synchronization data which allows
+
available at all times. Therefore, the BTS transmits synchronization
the MS to synchronize in time and frequency to its serving BTS. Each cellular standard
+
data which allows the MS to synchronize in time and frequency to its
(GSM, UMTS, LTE) has its own set of synchronization signals. In this
+
serving BTS. Each cellular standard (GSM, UMTS, LTE) has its own set
work, the case for LTE and LTE-Advanced shall be analyzed. A selection
+
of synchronization signals. In this work, the case for LTE and
of synchronization algorithms shall be compared during simulation. The
+
LTE-Advanced shall be analyzed.
so found best algorithm shall be implemented in VHDL. The resulting code
 
can then be mapped onto an FPGA testbed or it can be used for an ASIC design.
 
  
===Status: Available ===
+
LTE synchronization consists of 4 parts:
: Looking for 1-2 Semester/Master students
+
# LTE center frequency detection.
: Contact: [http://www.iis.ee.ethz.ch/portrait/staff/weberbe.en.html Benjamin Weber]
+
# OFDM symbol timing and fractional frequency offset detection.
===Prerequisites===
+
# LTE specific Primary Synchronization Sequence (PSS) detection.
: VLSI I
+
# LTE specific Secondary Synchronization Sequence (SSS) detection.
: Interest in Mobile Communication
+
During this project, the student is asked to find a complete
 +
synchronization approach for the LTE system and test it on an RF/FPGA
 +
testbed. The testbed includes an RF chip connected to an FPGA which in
 +
turn is connected to a PC.
 
<!--  
 
<!--  
 
===Status: Completed ===
 
===Status: Completed ===
Line 27: Line 28:
 
: Matthias Baer, Renzo Andri
 
: Matthias Baer, Renzo Andri
 
--->
 
--->
<!--
 
 
===Status: In Progress ===
 
===Status: In Progress ===
: Student A, StudentB
+
: Student: Elis Nycander
: Supervision: [[:User:Mluisier | Mathieu Luisier]]
+
: Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Belfanti|Sandro Belfanti]]
--->
 
===Character===
 
: 20% Theory
 
: 40% Matlab simulation
 
: 40% FPGA or ASIC design
 
  
 
===Professor===
 
===Professor===
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
 
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
+
 
<!-- : [http://www.nano-tcad.ethz.ch/en/general-information/people/professors/uid/6326.html Mathieu Luisier] --->
 
<!-- : [http://www.nano-tcad.ethz.ch/en/general-information/people/professors/uid/1021.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]
 
[[Category:Analog]]
 
[[Category:Analog]]
[[Category:Available]]
+
[[Category:In progress]]
[[Category:Semester Thesis]]
 
 
[[Category:Master Thesis]]
 
[[Category:Master Thesis]]
 +
[[Category:FPGA]]
 +
[[Category:Telecommunications]]
 +
[[Category:Weberbe]]
 +
[[Category:Belfanti]]
  
 
<!--  
 
<!--  
Line 57: Line 51:
 
GROUP
 
GROUP
 
[[Category:Digital]]
 
[[Category:Digital]]
 +
    SUB CATEGORIES
 +
    [[Category:ASIC]]
 +
    [[Category:FPGA]]
 +
    [[Category:Cryptography]]
 +
    [[Category:System Design]]
 +
    [[Category:Processor]]
 +
    [[Category:Telecommunications]]
 +
    [[Category:System Design]]
 +
    [[Category:Modelling]]
 +
 +
 
[[Category:Analog]]
 
[[Category:Analog]]
 
[[Category:Nano-TCAD]]
 
[[Category:Nano-TCAD]]
Line 88: Line 93:
 
[[Category:2013]]
 
[[Category:2013]]
 
[[Category:2014]]
 
[[Category:2014]]
 +
[[Category:2015]]
  
 
--->
 
--->

Revision as of 16:36, 5 February 2015

LTE Synchronization.png

Short Description

Wireless communication imposes immense challenges on receiver design in case the transmitter and receiver are not synchronized. Strongly centralized network topologies such as cellular communication networks rely on high-quality hardware at the base transceiver station (BTS). This allows the network to be in sync with a common external signal (such as GPS). On the Mobile Station (MS) side, however, it cannot be guaranteed that such an external common clock signal is available at all times. Therefore, the BTS transmits synchronization data which allows the MS to synchronize in time and frequency to its serving BTS. Each cellular standard (GSM, UMTS, LTE) has its own set of synchronization signals. In this work, the case for LTE and LTE-Advanced shall be analyzed.

LTE synchronization consists of 4 parts:

  1. LTE center frequency detection.
  2. OFDM symbol timing and fractional frequency offset detection.
  3. LTE specific Primary Synchronization Sequence (PSS) detection.
  4. LTE specific Secondary Synchronization Sequence (SSS) detection.

During this project, the student is asked to find a complete synchronization approach for the LTE system and test it on an RF/FPGA testbed. The testbed includes an RF chip connected to an FPGA which in turn is connected to a PC.

Status: In Progress

Student: Elis Nycander
Supervision: Benjamin Weber, Sandro Belfanti

Professor

Qiuting Huang