Difference between revisions of "ASIC Design Projects"
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* At the end of the semester (or as soon as there is an opportunity) we will send the chip to fabrication | * At the end of the semester (or as soon as there is an opportunity) we will send the chip to fabrication | ||
* A typical semester thesis takes 14 weeks, chips need another 15-16 weeks until they come back from manufacturing | * A typical semester thesis takes 14 weeks, chips need another 15-16 weeks until they come back from manufacturing | ||
− | * You can test it as part of [http://vlsi3.ethz.ch vlsi3] or a separate project. | + | * You can test it as part of [http://vlsi3.ethz.ch vlsi3] or a separate project. |
=== Why is it a good idea=== | === Why is it a good idea=== |
Latest revision as of 18:13, 29 January 2021
Design your ASIC
How does it work
You want to do your very own ASIC, great. Here are some simple steps:
- You need to attend VLSI2 and most importantly follow the exercises. They are step by step guides in making your own chip
- You can register to a ASIC semester thesis together with VLSI2 or any following semester, or even do it as part of a master thesis
- It is best if the work is done in groups of two
- At the end of the semester (or as soon as there is an opportunity) we will send the chip to fabrication
- A typical semester thesis takes 14 weeks, chips need another 15-16 weeks until they come back from manufacturing
- You can test it as part of vlsi3 or a separate project.
Why is it a good idea
- There are only very few universities you can do something like this
- This is a real project that will allow you to learn how to manage the design of complex systems in practice.
- It looks great on your CV
Newly available ASIC design projects from our group
- Event-Driven Convolutional Neural Network Modular Accelerator
- Spiking Neural Network for Autonomous Navigation
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
Available ASIC design projects from our group
No pages meet these criteria.
Old ASIC design projects ideas from our group
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Single-Bit-Synapse Spiking Neural System-on-Chip
Links
- See the main page for all our projects
- Visit our chip gallery to see what other students have done in recent years
- See the EDA wiki page for technical information (accessible only within ETH VPN)