ASIC Design of a Gaussian Message Passing Processor

Gaussian Message Passing can be used to formulate a wide range of real-world signal processing algorithms such as channel-estimation, equalization or time of arrival estimation. Recently we demonstrated, how a systolic array can be used to build a processor architecture to efficiently run such algorithms [1]. A specific processor of this type is usually attached as a fixed-function-unit to a heterogeneous multicore processor.

The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab model and extend it with a single instruction, multiple data (SIMD) operation mode. Then you will compare the performance speed-up for parallel execution against the existing architecture and start with the back-end design. After the back-end, the final ASIC will be fabricated in high-end CMOS technology.