Personal tools

Difference between revisions of "ASIC Development of 5G-NR LDPC Decoder"

From iis-projects

Jump to: navigation, search
 
(25 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
[[File:5G.jpeg|thumb|400px|5G Communication, Source: https://medium.com]][[File:5G_LDPC.jpg|thumb|400px|5G LDPC Codes, Source: IEEE Access, DOI: 10.1109/ACCESS.2018.2868963.]]
 
[[File:5G.jpeg|thumb|400px|5G Communication, Source: https://medium.com]][[File:5G_LDPC.jpg|thumb|400px|5G LDPC Codes, Source: IEEE Access, DOI: 10.1109/ACCESS.2018.2868963.]]
==Short Description==
+
==Introduction==
 
Error-correcting codes enable the correction of transmitted bits received over noisy channels and thus are vital for the contemporary wireless communication systems. Low-Density Parity-Check (LDPC) codes represent a class of high-performance error-correcting codes, and therefore, have been adopted for data transmission in the 5G New-Radio (NR). VLSI implementation of the 5G-NR LDPC decoder is a challenging task because it is defined to support large number of case scenarios for low latency on one hand and high decoding performance on the other side. It is worth working with VLSI implementation of 5G-NR LDPC codes because of their practical relevance and high demand for the 5G wireless communication systems.
 
Error-correcting codes enable the correction of transmitted bits received over noisy channels and thus are vital for the contemporary wireless communication systems. Low-Density Parity-Check (LDPC) codes represent a class of high-performance error-correcting codes, and therefore, have been adopted for data transmission in the 5G New-Radio (NR). VLSI implementation of the 5G-NR LDPC decoder is a challenging task because it is defined to support large number of case scenarios for low latency on one hand and high decoding performance on the other side. It is worth working with VLSI implementation of 5G-NR LDPC codes because of their practical relevance and high demand for the 5G wireless communication systems.
  
Line 10: Line 10:
 
* Synthesis of the developed RTL code
 
* Synthesis of the developed RTL code
 
* Placement and routing of the synthesized design
 
* Placement and routing of the synthesized design
+
*      A chip tape out is possible if desired by the student
  
===Status: Available ===
+
===Status: Not Available ===
: Looking for Interested Master Students (Semester Project / Master Thesis)
+
: Contact: [[user:Susman | Saleh Usman]]
: Contact: [[User:susman | Saleh Usman]]
 
  
 
===Prerequisites===
 
===Prerequisites===
Line 26: Line 25:
  
 
===Professor===
 
===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
+
[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]
 
 
[[#top|↑ top]]
 
<!--
 
==Detailed Task Description==
 
 
 
===Goals===
 
===Practical Details===
 
* '''[[Project Plan]]'''
 
* '''[[Project Meetings]]'''
 
* '''[[Design Review]]'''
 
* '''[[Coding Guidelines]]'''
 
* '''[[Final Report]]'''
 
* '''[[Final Presentation]]'''
 
 
 
==Results==
 
 
 
==Links==
 
--->
 
[[#top|↑ top]]
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]
 +
[[Category:FPGA]]
 +
[[Category:Telecommunications]]
 +
[[Category:Bachelor Thesis]]
 +
[[Category:Semester Thesis]]
 
[[Category:Master Thesis]]
 
[[Category:Master Thesis]]
[[Category:Semester Thesis]]
+
[[Category:Susman]]
 
[[Category:Hot]]
 
[[Category:Hot]]
[[Category:Available]]
+
[[Category:In progress]]
[[Category:ASIC]]
 
[[Category:Telecommunications]]
 
[[Category:Susman]]
 
  
 
<!--  
 
<!--  
 
 
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES
 
COPY PASTE FROM THE LIST BELOW TO ADD TO CATEGORIES
  
Line 78: Line 58:
  
 
STATUS
 
STATUS
[[Category:Available]]
 
 
[[Category:In progress]]
 
[[Category:In progress]]
 
[[Category:Completed]]
 
[[Category:Completed]]
Line 99: Line 78:
  
 
YEAR (IF FINISHED)
 
YEAR (IF FINISHED)
[[Category:2010]]
+
[[Category:2021]]
[[Category:2011]]
 
[[Category:2012]]
 
[[Category:2013]]
 
[[Category:2014]]
 
[[Category:2015]]
 
[[Category:2016]]
 
  
 
--->
 
--->

Latest revision as of 00:43, 10 February 2021

5G Communication, Source: https://medium.com
5G LDPC Codes, Source: IEEE Access, DOI: 10.1109/ACCESS.2018.2868963.

Introduction

Error-correcting codes enable the correction of transmitted bits received over noisy channels and thus are vital for the contemporary wireless communication systems. Low-Density Parity-Check (LDPC) codes represent a class of high-performance error-correcting codes, and therefore, have been adopted for data transmission in the 5G New-Radio (NR). VLSI implementation of the 5G-NR LDPC decoder is a challenging task because it is defined to support large number of case scenarios for low latency on one hand and high decoding performance on the other side. It is worth working with VLSI implementation of 5G-NR LDPC codes because of their practical relevance and high demand for the 5G wireless communication systems.

Project Description

The goal of this project is to develop an efficient ASIC for a 5G-NR LDPC decoder. We will start by proposing an efficient architecture for the 5G-NR LDOC decoder and then implement it using HDL. The developed HDL code will be synthesized and implemented as an ASIC after placement and routing. The breakdown of the tasks will be as follows:

  • Propose architecture for 5G LDPC decoder
  • RTL implementation of the proposed architecture
  • Synthesis of the developed RTL code
  • Placement and routing of the synthesized design
  • A chip tape out is possible if desired by the student

Status: Not Available

Contact: Saleh Usman

Prerequisites

An interest in digital signal processing
Knowledge in Verilog/VHDL

Character

20% Modeling of 5G LDPC decoder in MATLAB/C/Cpp
40% Verilog/VHDL implementation
40% ASIC design

Professor

Qiuting Huang