Difference between revisions of "ASIC Implementation of High-Throughput Next Generation Turbo Decoders"
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: Looking for 1-2 Semester/Master students | : Looking for 1-2 Semester/Master students | ||
: Contact: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti] | : Contact: [http://iis-projects.ee.ethz.ch/index.php/User:Belfanti Sandro Belfanti] | ||
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: VLSI I | : VLSI I | ||
: MATLAB and VHDL is an advantage | : MATLAB and VHDL is an advantage | ||
Revision as of 10:15, 17 January 2014
Contents
Short Description
Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile communications, most modern systems rely on turbo codes because of their outstanding error correction capabilities in conjunction with efficient decoder implementations. For the most recently developed standards with throughput requirements in excess of 1Gbps, providing the necessary throughput has become a real challenge. The IIS has a long history of high-throughput turbo decoders and we have recently had several new ideas on how to improve our architectures even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, you can rely on the expertise from a long line of previous turbo decoders to hopefully develop an outstanding ASIC.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Sandro Belfanti
Prerequisites
- VLSI I
- MATLAB and VHDL is an advantage
Character
- 20% Simulation/Theory
- 50% VHDL
- 30% ASIC Implemenatation
