ASIC Implementation of High-Throughput Next Generation Turbo Decoders
Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile communications, most modern systems rely on turbo codes because of their outstanding error correction capabilities in conjunction with efficient decoder implementations. For the most recently developed standards with throughput requirements in excess of 1Gbps, providing the necessary throughput has become a real challenge. The IIS has a long history of high-throughput turbo decoders and we have recently had several new ideas on how to improve our architectures even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, you can rely on the expertise from a long line of previous turbo decoders to hopefully develop an outstanding ASIC.
If you are interested in doing a thesis (semester or master) in the field of error correcting codes, such as turbo codes, just contact Sandro Belfanti or Christoph Roth. There are different projects available, ranging from more theoretical/simulation based projects to the VLSI implementation in form of chip design projects.
Previous Turbo Decoders
All the chips which have been fabricated can be found in the IIS chip gallery. Some examples for turbo decoders designed at the IIS are
- Looking for 1-2 Semester/Master students
- Contact: Sandro Belfanti
- VLSI I
- MATLAB and VHDL is an advantage
- 20% Simulation/Theory
- 50% VHDL
- 30% ASIC Implemenatation