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[[File:jammer_mitigation_asic.png|400px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]
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[[File:jammer_mitigation_asic.png|380px|thumb|A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.]]
 
==Short Description==
 
==Short Description==
  
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Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements).  
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Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms.  
  
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Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.
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The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.
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[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.
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[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.
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[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.
  
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The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.
 
  
 
===Status: Available ===
 
===Status: Available ===
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: Looking for a Semester/Master student
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: Looking for 1-2 Semester/Master students
 
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]
 
: Contact: [https://iip.ethz.ch/people/profiles.MTk4MzMz.TGlzdC80MTExLDEwNjY3Mjg3NDU=.html Gian Marti]
  
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==Links==  
 
==Links==  
  
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[[Category:Available]]
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[[Category:Completed]]
 
[[Category:IIP]]
 
[[Category:IIP]]
 
[[Category:IIP_5G]]
 
[[Category:IIP_5G]]
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[[Category:2022]]
  
 
[[#top|↑ top]]
 
[[#top|↑ top]]

Latest revision as of 12:31, 10 May 2023

A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.

Short Description

Jamming attacks pose a critical threat to wireless communication systems. Multi-antenna (MIMO) wireless systems have the potential to mitigate such jamming attacks through signal processing. Methods for jammer mitigation are thus currently a hot research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms have been proposed. To be practically viable, such methods will ultimately have to be implemented in hardware (using FPGAs or, more likely, ASICs), since sofware-based signal processing will never support the data rates of modern wireless systems. To this date, however, there are no hardware implementations of jammer mitigation algorithms.

The goal of this project is to develop the first ASIC implementation of a jammer-mitigating signal processing algorithm. For this, the student will take a state-of-the art jammer mitigation algorithm and adapt it as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.


[1] Q. Yan, H. Zeng, T. Jiang, M. Li, W. Lou, and Y. T. Hou "Jamming resilient communication using MIMO interference cancellation." IEEE Transactions on Information Forensics and Security 11(7), 2016, 1486-1499.

[2] H. Akhlaghpasand, E. Björnson, and S. Mohammad Razavizadeh. "Jamming suppression in massive MIMO systems." IEEE Transactions on Circuits and Systems II: Express Briefs 67(1), 2019, 182-186.

[3] T. Erpek, Y. E. Sagduyu, and Y. Shi. "Deep learning for launching and mitigating wireless jamming attacks." IEEE Transactions on Cognitive Communications and Networking 5(1), 2018, 2-14.


Status: Available

Looking for 1-2 Semester/Master students
Contact: Gian Marti

Prerequisites

Verilog or VHDL
VLSI II
Familiarity with the basics of digital communication is recommended but not strictly required

Character

80% VLSI Implementation and Verification
20% MATLAB simulation

Professor

Christoph Studer

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