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ASIC Implementation of Jammer Mitigation

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A MIMO basestation mitigates an ongoing jamming attack while continuing to serve the legitimate user equipments. The signal processing for this takes place in a custom ASIC.

Short Description

Wireless communication networks are an important part of modern infrastructure, and their continuous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt communication by injecting interference signals. In this project, we consider a scenario in which user equipments (UEs) try---in the presence of a jamming attack---to transmit data to a cellular basestation that employs massive multi-antenna (MIMO) technology (i.e., a basestation with a large number of antenna elements).

Some types of jamming attacks are straightforward to deal with: If the jammer is steadily transmitting, a protocol can be implemented that detects its transmit signature. The BS can then cancel the jammer's signal with simple but effective linear cancellation techniques in order to obtain the jammer-free UE signals. Things are not so simple in practice, however, when the jammer is "smart": Whenever the basestation tries to learn the jammer's signature the jammer might simply stop transmitting, only getting active when the UEs try to transmit their data.

The goal of this project is to develop new algorithms for jammer mitigation that abandon the assumption of a steadily transmitting jammer by using recently developed nonlinear signal processing algorithms developed in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics and linear algebra. Some familiarity with wireless communication and numerical optimization would be beneficial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging paradigm to tune iterative algorithms with deep learning methods, as a means to improve the algorithms' performance or to reduce its complexity.

Status: Available

Looking for a Semester/Master student
Contact: Gian Marti


Verilog or VHDL
Familiarity with the basics of digital communication is recommended but not strictly required


80% VLSI Implementation and Verification
20% MATLAB simulation


Christoph Studer

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Detailed Task Description


Practical Details



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