ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
Beamspace processing for mmWave massive multiple-input multiple-output (MIMO) systems is a recent paradigm for low-power implementation of digital baseband processing. Many baseband processing tasks are composed of matrix multiplications that need to be performed with high throughput and at low latency. In the beamspace-domain, these matrices are approximately sparse, allowing for a reduction of the average number of multiplications performed per second [1,2]. For uplink data detection and downlink precoding, we have recently designed algorithms that generate strictly sparse equalization and precoding matrices [3,4]. However, to transfer the data from antenna-domain into beamspace-domain, a discrete Fourier transform (DFT) need to be applied to each of the antenna-domain quantities, resulting in higher dynamic range after the transform. This creates a problem for fixed-point implementation, as it requires larger word lengths resulting in larger area and power consumption, which works against the initial purpose of beamspace processing. Unfortunately, even the simplest floating point formats, such as bfloat16, result in inefficient hardware for the extremely high-throughput and power-hungry operations required for baseband processing.
In this project, we investigate a novel idea to overcome the curse of precision growth in the beamspace-domain. The idea is to use a custom floating-point format that keeps the multiplication and addition operations as simple as possible, while offering greater flexibility for representing high dynamic range numbers arising in beamspace processing. This approach can help to reduce the total number of bits compared to the standard two’s complement fixed-point format, and therefore the area and power of the matrix multiplication can be reduced. We will design specialized multipliers that take operands in this custom floating-point format. This new approach will be simulated in MATLAB for a mmWave massive MIMO system and the optimal number format parameters are chosen. Then, a matrix-vector product engine will be implemented in Verilog and the corresponding ASIC will be implemented. The goal is to explore the area and power savings achieved by this technique by performing the backend and doing power simulations using IC design tools. As the starting point, we will use our SPADE matrix-vector product engine which is designed based on the idea proposed in .
The ideas of this project can be extended to other system blocks such as the beamspace FFT, so that these blocks generate their outputs directly in the proposed custom format and thus eliminate the need for a conversion step to convert the data from fixed-point to the custom floating point format.
 S. H. Mirfarshbafan and C. Studer, "SPADE: Sparsity-Adaptive Equalization for MMwave Massive MU-MIMO," IEEE Statistical Signal Processing Workshop (SSP), 2021
 S. H. Mirfarshbafan, A. Gallyas-Sanhueza, R. Ghods and C. Studer, "Beamspace Channel Estimation for Massive MIMO mmWave Systems: Algorithm and VLSI Design," IEEE Transactions on Circuits and Systems I, Dec. 2020
 S. H. Mirfarshbafan and C. Studer, "Sparse Beamspace Equalization for Massive MU-MIMO MMWave Systems," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020
 E. Gönültaş, S. Taner, A. Gallyas-Sanhueza, S. H. Mirfarshbafan and C. Studer, "Hardware-Aware Beamspace Precoding for All-Digital mmWave Massive MU-MIMO," IEEE Communications Letters, Nov. 2021
- Semester or master project for 1-2 students
- Contact: Seyed Hadi Mirfarshbafan
- Verilog or VHDL
- VLSI II
- 80% VLSI implementation
- 20% MATLAB simulation