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Active-Set QP Solver on FPGA

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Short Description

The master thesis will be carry on in collaboration with ABB CHCRC and will focus on the implementation of an Active-Set quadratic program (QP) solver accelerator on FPGA.

QP problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but their use on FPGAs is considered challenging as they rely on more involved linear algebra operations such as matrix factorizations. Aim of this thesis project is to investigate the potential of implementing an active-set method for FPGAs and to identify/adapt an existing scheme to be implemented in hardware.

Status: Available

Looking for Interested Students
Type: Master Thesis
Supervisors: Andrea Bartolini, Michael Schaffner


VLSI I, VLSI II, Control Systems
Matlab, C++, VHDL or System Verilog


20% Theory
60% Implementation
20% Testing


ABB Corporate Research Center (CHCRC)


Luca Benini

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