Personal tools

Difference between revisions of "Active-Set QP Solver on FPGA"

From iis-projects

Jump to: navigation, search
m (Short Description)
 
(5 intermediate revisions by the same user not shown)
Line 12: Line 12:
  
 
===Prerequisites===
 
===Prerequisites===
: VLSI I, VLSI II
+
: VLSI I, VLSI II, Control Systems
: Control Systems
+
: Matlab, C++, VHDL or System Verilog
  
 
===Character===
 
===Character===
Line 19: Line 19:
 
: 60% Implementation
 
: 60% Implementation
 
: 20% Testing
 
: 20% Testing
 +
 +
===Partners===
 +
: [http://www.abb.ch/cawp/abbzh254/ec72bb280fd24d47c1256b5700522f3a.aspx ABB Corporate Research Center (CHCRC)]
  
 
===Professor===
 
===Professor===
Line 43: Line 46:
  
  
[[Category:Hot]] [[Category:Digital]] [[Category:Master Thesis]] [[Category:Available]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:SBB CHCRC]] [[Category:Model Predictive Controller]]
+
[[Category:Hot]] [[Category:Digital]] [[Category:Master Thesis]] [[Category:Completed]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Controller]] [[Category: 2015]]

Latest revision as of 12:09, 2 November 2015

TeaserAbb.png

Short Description

The master thesis will be carry on in collaboration with ABB CHCRC and will focus on the implementation of an Active-Set quadratic program (QP) solver accelerator on FPGA.

QP problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but their use on FPGAs is considered challenging as they rely on more involved linear algebra operations such as matrix factorizations. Aim of this thesis project is to investigate the potential of implementing an active-set method for FPGAs and to identify/adapt an existing scheme to be implemented in hardware.

Status: Available

Looking for Interested Students
Type: Master Thesis
Supervisors: Andrea Bartolini, Michael Schaffner

Prerequisites

VLSI I, VLSI II, Control Systems
Matlab, C++, VHDL or System Verilog

Character

20% Theory
60% Implementation
20% Testing

Partners

ABB Corporate Research Center (CHCRC)

Professor

Luca Benini

↑ top

Detailed Task Description

Goals

Practical Details

Results