Personal tools

Difference between revisions of "Active-Set QP Solver on FPGA"

From iis-projects

Jump to: navigation, search
(Short Description)
(Short Description)
Line 25: Line 25:
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
[[#top|↑ top]]
 
[[#top|↑ top]]
 +
[[File:teaserAbb.pdf]]
  
 
==Detailed Task Description==
 
==Detailed Task Description==

Revision as of 11:10, 12 January 2015

Short Description

The master thesis will be carry on in collaboration with ABB CHCRC and will focus on the implementation of an Active-Set QP solver accelerator on FPGA.

Quadratic programming (QP) problems arise in various embedded optimization applications such as model predictive control or constrained least-square fitting. Various solution algorithms have been proposed and implemented on CPUs (some of them also on FPGAs), each of them exhibiting specific advantages and drawbacks. Active-set methods are frequently used on CPUs for solving QPs efficiently, but their use on FPGAs is considered challenging as they rely on more involved linear algebra operations such as matrix factorizations. Aim of this thesis project is to investigate the potential of implementing an active-set method for FPGAs and to identify/adapt an existing scheme to be implemented in hardware.

Status: Available

Looking for Interested Students
Supervisors: Andrea Bartolini, Michael Shaffner

Prerequisites

VLSI I, VLSI II
Control Systems

Character

20% Theory
60% Implementation
20% Testing

Professor

Luca Benini

↑ top File:TeaserAbb.pdf

Detailed Task Description

Goals

Practical Details

Results