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| − | [[Category:Digital]] | + | #REDIRECT [[Adding Linux Support to our DMA Engine (1-2S/B)]] |
| − | [[Category:High Performance SoCs]]
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| − | [[Category:Computer Architecture]]
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| − | [[Category:2021]]
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| − | [[Category:Semester Thesis]]
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| − | [[Category:Bachelor Thesis]]
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| − | [[Category:Tbenz]]
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| − | [[Category:Michaero]]
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| − | [[Category:Available]]
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| − | == Introduction ==
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| − | At IIS we are developing a modular and extensible high-performance direct memory access (DMA) engine. So far we have integrated it in our cluster-based systems. On those systems are programmed using bare-metal code to achieve the highest energy efficiency.
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| − | Next to the cluster-based systems, we are working on Ariane (CVA6), a 64 bit application-grade linux-capable core.
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| − | We are now planning to integrate our DMA engine in an Ariane-based SoC and evaluate its benefits in a Linux environment.
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| − | == Project ==
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| − | We propose to divide the project in these steps:
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| − | * '''Research''': Investigate how Linux interacts with a system-level DMA and collect a set of minimal requirements for the hardware.
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| − | * '''RTL design''': Create a hardware interface for the DMA engine that features this set of minimal requirements Linux opposes on the hardware.
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| − | * '''Validation and driver development''': Create a driver for Linux allowing it to interface with the DMA; validate your hardware using simple transfers
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| − | * '''Evaluation''': Run complex applications to evaluate the performance of the DMA in this context.
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| − | == Requirements ==
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| − | * Experience with digital design in SystemVerilog as taught in VLSI I
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| − | == Composition ==
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| − | * 30% studying the DMA interface imposed by Linux
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| − | * 20% RTL design
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| − | * 30% driver development & validation
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| − | * 10% evaluation
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| − | == Project Supervisors ==
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| − | * [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]
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| − | * [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]
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