View source for An Efficient Compiler Backend for Snitch (1S/B)

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[[Category:Digital]]
[[Category:High Performance SoCs]]
[[Category:Computer Architecture]]
[[Category:2022]]
[[Category:Semester Thesis]]
[[Category:Master Thesis]]
[[Category:Paulsc]]
[[Category:Balasr]]
[[Category:Available]]


= Overview =

== Status: Available ==

* Type: Semester or Bachelor Thesis
* Professor: Prof. Dr. L. Benini
* Supervisors:
** [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]
** [[:User:Balasr | Robert Balas]]: [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch]

= Introduction =

The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the minimal RISC-V Snitch integer core, only about 15 kilogates in size, which can optionally be coupled to accelerators such as an FPU or a DMA engine.

Snitch’s floating-point subsystem is highly interesting: it includes stream semantic registers (SSRs) [2] and the floating-point repetition (FREP) hardware loop, enabling almost 100% FPU utilization in many data-oblivious problems with regular access patterns.

Recently, we have explored compiler support for our SSR and FREP architecture extensions above. We find that in compiled code, the benefits of our extensions are held back by bad instuction scheduling, leading to unnecessary stalls and thus performance losses compared to hand-written assembly kernels.

= Project =

In this project, you will optimize the RISC-V compiler backend for Snitch, building on our existing fork of the LLVM RISC-V toolchain [3]. This will entail

* Familiarizing yourself with the LLVM RISC-V backend and our Snitch extensions for it so far.
* Analyzing the inefficiencies and bottlenecks in compiled benchmarks using the current backend.
* Extending and tuning the Snitch machine scheduler to reflect the hardware as accurately as possible.
* Further tuning the scheduling to improve extension performance
* Evaluating the new backend against the existing one on various compiled benchmarks in cycle-accurate simulation.

== Character ==

* 20% Code / Architecture review
* 40% Compiler design
* 20% Bare-metal C programming
* 20% Performance evaluation

== Prerequisites ==

* Knowledge of or prior experience with compiler backend design
* Strong interest in computer architecture
* Preferred: Knowledge of or prior experience with digital design as taught in VLSI 
* Preferred: Knowledge of or prior experience with RISC-V or ISA extension design

= References =

[1] https://ieeexplore.ieee.org/document/9068465

[2] https://ieeexplore.ieee.org/document/8980305

[3] https://github.com/pulp-platform/llvm-project