An FPGA-Based Testbed for 3G Mobile Communications Receivers
In this project you will develop and FPGA-based testbed for the 3G standard TD-SCDMA, with the option to extend it with an ASIC in the future. The digital baseband receiver already exists at the IIS, although without any realistic interfaces to frontend and higher layers. These interfaces will be written as part of this project. The goal is to map the existing receiver ASIC to an FPGA and devise a testbed including the analog frontend (which will be provided) as well as a micro controller board for easy access from a PC. To that end the existing receiver has to be extended to include a digital frontend as well as means to communicate with the micro controller.
Status: In Progress
- Supervision: Sandro Belfanti
- VLSI I
- MATLAB and VHDL is an advantage
- Interest in Mobile Communications