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Augmenting Our IPs with AXI Stream Extensions (M/1-2S)

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Status: Reserved


General-purpose processors often access data as memory streams, or sequences of memory requests following a predefined address pattern. Recent architectural extensions [1,2] propose handling such streams in hardware, which brings many benefits: it frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also decouples data movement from execution, hiding architectural latencies and maximizing bandwidth utilization.

We recently began exploring how to leverage the benefits of memory streams in large Systems on Chip (SoCs) by propagating their semantics (address pattern information such as loop bounds and strides) throughout the memory system. To this end, we are currently extending the AXI4 [3] memory protocol, used in many of our IPs, to support affine (strided) and indirect streams, the most common stream types in real-world applications [2].

Now, we would like to make use of this extended protocol in our existing AXI4 IPs to improve their performance, as well as fully quantify its benefits. We would also like to demonstrate the extensions in a full demonstrator SoC.


In this project, you will extend some of our existing core, interconnect, and memory IPs to properly handle our AXI4 stream extensions. We will first focus on

  • Our existing AXI4 interconnect IP suite [4] (crossbars, buffers, converters, serializers, ...)
  • Our universal Direct Memory Access (DMA) engine
  • Our banked AXI4 on-chip memories

Depending on the remaining time and your personal interests, further IPs can extended and investigated, for example:

  • Our vector processor Ara [5]
  • Our last-level and read-only caches
  • Our AXI4 off-chip serial link

A simple demonstrator system building on your extended IPs could also be built.


  • 20% Architecture & spec review
  • 40% RTL implementation
  • 20% Verification
  • 20% Evaluation


  • Strong interest in computer architecture and memory systems
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with ASIC implementation flow (synthesis) or parallel enrolment in VLSI II
  • Preferred: SoCs for Data Analytics and ML and/or Computer Architecture lectures
  • Preferred: Knowledge or experience with AXI and RISC-V