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Baseband Meets CPU

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Vision of modem SoC (external power amplifier not shown). The bold interfaces can be implemented during this project.
Testbed setup with L2/L3 processing on ZedBoard (top), double RF on EvalEDGE v1.0 (middle), and DBB on ML605 (bottom).


Emerging applications for the Internet-of-Things (IoT) or Machine-to-Machine (M2M) devices always require some type of communication interface with the rest of the world. Due to its ubiquitous coverage, the 2G cellular standard GSM and its enhancements are good candidates for the communication interface. Whenever a power plug is not an option ultra long battery life is a key requirement. And, as the number of IoT nodes increases ultra low cost per node is yet another requirement. In order to comply with IoT node requirements high integration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are used. In order to reach this goal the current single chip 2G PHY developed at the institute shall be enhanced with a L2/L3 CPU.

Project Description

A cellular modem consists of various portions:

  • Radio Frequency (RF) analog processing
  • Digital Baseband (DBB) processing
  • L2/L3 processing on CPU.

The DBB block has been integrated at the institute in the RazorEDGE project [2]. The RF chip comes from project partner ACP and RazorEDGE DBB have been combined and integrated in the StoneEDGE project. This master thesis project combines the two digital blocks, RazorEDGE DBB and PULP CPU. The PULP CPU architecture has been developed at the institute. In the future, all three modem components (RF, DBB, CPU) shall be combined into a single modem SoC. The number of cores within the PULP CPU can be adapted to the required needs. A possible setup is two use two cores, one for L2/L3 processing and another for voice codec processing in the case of a mobile phone application or data processing in the case of an IoT/M2M application.

The RazorEDGE (and StoneEDGE) control interface has been designed having a separate chip as controlling instance in mind. In particular, a Serial Peripheral Interface (SPI) is used. As the controlling instance (PULP CPU) will now be on the same die, a custom parallel interface between the PULP CPU and the RazorEDGE DBB is required.

Furthermore, a modem SoC requires a number of I/O interfaces in order to function properly. Not all interfaces are required for all applications.

Antenna I/O
The antenna port is taken care of by the RF part.
A number of General Purpose Inputs/Outputs (GPIOs) are present in every cellular modem. They can be used for e.g. time critical control bits steering an external power amplifier. GPIOs have already been integrated into the RazorEDGE DBB and are programmable over the RazorEDGE control interface.
Boot loader I/O
The boot loader I/O can use an already existing interface (e.g. SPI) of the PULP CPU architecture. ;Modem control/data I/O: This is the interface to external applications which desire to use the modem for communication purposes. A standardized serial interface called HSI is available for this purpose [3]. For ultra-low footprint IoT/M2M applications modem control/data I/O can be omitted by having a proper ADC I/O and an extra IoT/M2M core within the modem SoC for data processing.
SIM-Card I/O
Irrespective of the target application (cellular phone or IoT/M2M) a modem SoC needs a SIM-card to function properly. Relevant standards can be found on the ETSI website [4,5]. Digital audio I/O: It is possible to transfer a digital audio stream over the modem control/data I/O. However, a separate stream based digital audio interface is better suited for this purpose. If an IoT/M2M application is targeted an audio interface is not required.
Almost any IoT/M2M application employs some sort of analog data acquisition, e.g. a temperature or humidity sensor. An ADC samples the analog signal and forwards it to a CPU for further processing. The prepared data gets forwarded to the modem SoC through the modem control/data I/O for wireless transmission. Alternatively, an ADC can be directly connected to the modem SoC and an extra IoT/M2M core within the modem SoC processes the data before transferring it to the L2/L3 core. Of course, for pure cellular phone applications an ADC I/O is not required.

Both the digital audio I/O and the ADC I/O require external ADC/DAC components. Alternatively, a suitable ADC/DAC can be integrated into the modem SoC thus lowering component count and footprint area. But, a modem SoC internal digital audio I/O or ADC I/O would still be required.

A functional RF/FPGA testbed is available which distributes modem tasks over three separate boards. These are

  • Double RF on IIS EvalEDGE v1.0 board
  • DBB on Virtex-6 FPGA on ML605 board (see [6])
  • L2/L3 processing on ARM core on ZedBoard (see [7])

The testbed shall be used during this project in order to test the combined DBB and PULP on the Virtex-6 FPGA together with the double RF evalEDGE v.1.0 board. The ZedBoard can be used for controlling or monitoring.

Status: Completed

Student: Mauro Salomon (msc15f2)
Supervision: Benjamin Weber, Pirmin Vogel, Frank K. Gurkaynak


Qiuting Huang


[1] Sierra Wireless. AirPrime WS6318., January 2015.

[2] Harald Kröll, Stefan Zwicky, Benjamin Weber, Christoph Roth, Christian Benkeser, Andreas Burg, and Qiuting Huang. An evolved EDGE PHY ASIC supporting soft-output equalization and RX diversity. In European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014-40th, pages 203–206. IEEE, 2014.

[3] MIPI Alliance. High-speed Synchronous Serial Interface (HSI) Specification., January 2015.

[4] ETSI. Smart Cards., January 2015.

[5] ETSI. SIM., January 2015.

[6] XILINX. Virtex-6 FPGA ML605 Evaluation Kit., January 2015.

[7] AVNET. ZedBoard., January 2015.