Difference between revisions of "Beat Cadence"
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Revision as of 11:41, 18 January 2018
The so called Internet of Things (IoT) is expected to consist of multiple Billion devices by 2020. In such a projection only low-cost and low-power devices are sustainable. To this end, the Integrated System Laboratory (IIS) is together with the industry partner Advanced Circuit Pursuit (ACP) developing a highly integrated SoC for the IoT in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost as well as power consumption show room for improvement.
The goal of this project is to thoroughly analyze an important block in the targeted IoT SoC responsible for synchronization and repetition combining which is currently written using a High Level Synthesis (HLS) approach with Cadence tools. But, a hand-engineered digital architecture is expected to integrate the same functionality occupying less area and consume less power. Therefore, the HLS block will be redesigned using VHDL. Depending on the students interest an ASIC design can be targeted or an FPGA platform can be used for fast prototyping using e.g. the evalEDGE platform. This project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a machine.
- Looking for interested students for a Semester Project
- Contact: Benjamin Weber
- Interest in Digital Design or Communications
- VLSI I is plus
- 10% Theory, Algorithms and Simulation
- 70% Implementation (HLS/VHDL)
- 20% ASIC Implementation / FPGA Integration