http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&feed=atom&action=history
Beat Cadence - Revision history
2024-03-28T09:51:31Z
Revision history for this page on the wiki
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http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=4628&oldid=prev
Weberbe at 09:01, 18 March 2019
2019-03-18T09:01:06Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:01, 18 March 2019</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l7" >Line 7:</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>The goal of this project is to thoroughly analyze an important block in the targeted IoT SoC responsible for synchronization and repetition combining which is currently written using a High Level Synthesis (HLS) approach with Cadence tools. But, a hand-engineered digital architecture is expected to integrate the same functionality occupying less area and consume less power. Therefore, the HLS block will be redesigned using VHDL. Depending on the students interest an ASIC design can be targeted or an FPGA platform can be used for fast prototyping using e.g. the [[evalEDGE]] platform. This project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a machine.</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>The goal of this project is to thoroughly analyze an important block in the targeted IoT SoC responsible for synchronization and repetition combining which is currently written using a High Level Synthesis (HLS) approach with Cadence tools. But, a hand-engineered digital architecture is expected to integrate the same functionality occupying less area and consume less power. Therefore, the HLS block will be redesigned using VHDL. Depending on the students interest an ASIC design can be targeted or an FPGA platform can be used for fast prototyping using e.g. the [[evalEDGE]] platform. This project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a machine.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>===Status: <del class="diffchange diffchange-inline">Available </del>===</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>===Status: <ins class="diffchange diffchange-inline">Obsolete </ins>===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del class="diffchange diffchange-inline">: Looking for interested students for a Semester Project</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">===Prerequisites===</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">: Interest in Digital Design or Communications</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">: VLSI I is a plus</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">===Character===</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">: 10% Theory, Algorithms and Simulation</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">: 70% Implementation (HLS/VHDL)</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">: 20% ASIC Implementation / FPGA Integration</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">===Professor===</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">[[Category:Digital]]</del></div></td><td colspan="2"> </td></tr>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">[[Category:Telecommunications]]</del></div></td><td colspan="2"> </td></tr>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">[[Category:Semester Thesis]]</del></div></td><td colspan="2"> </td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Weberbe]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>[[Category:Weberbe]]</div></td></tr>
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Weberbe
http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=3287&oldid=prev
Weberbe at 09:44, 18 January 2018
2018-01-18T09:44:20Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:44, 18 January 2018</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Prerequisites===</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Interest in Digital Design or Communications</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Interest in Digital Design or Communications</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: VLSI I is plus</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: VLSI I is <ins class="diffchange diffchange-inline">a </ins>plus</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Character===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Character===</div></td></tr>
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Weberbe
http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=3286&oldid=prev
Weberbe at 09:41, 18 January 2018
2018-01-18T09:41:04Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:41, 18 January 2018</td>
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<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div><del style="font-weight: bold; text-decoration: none;">[[Category:Hot]]</del></div></td><td colspan="2"> </td></tr>
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Weberbe
http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=3055&oldid=prev
Weberbe: /* Project Description */
2017-11-06T09:24:52Z
<p><span dir="auto"><span class="autocomment">Project Description</span></span></p>
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:24, 6 November 2017</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: Looking for interested <del class="diffchange diffchange-inline">1-2 Master </del>students for a Semester Project</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: Looking for interested students for a Semester Project</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
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Weberbe
http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=3054&oldid=prev
Weberbe at 09:24, 6 November 2017
2017-11-06T09:24:29Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 09:24, 6 November 2017</td>
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<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>: Looking for 1-2 Semester <del class="diffchange diffchange-inline">students</del></div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>: Looking for <ins class="diffchange diffchange-inline">interested </ins>1-2 <ins class="diffchange diffchange-inline">Master students for a </ins>Semester <ins class="diffchange diffchange-inline">Project</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>: Contact: [[:User:Weberbe|Benjamin Weber]]</div></td></tr>
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Weberbe
http://iis-projects.ee.ethz.ch/index.php?title=Beat_Cadence&diff=3053&oldid=prev
Weberbe: Created page with "thumb == Introduction == The so called Internet of Things (IoT) is expected to consist of multiple Billion devices by 2020. In such a projection onl..."
2017-11-06T09:23:11Z
<p>Created page with "<a href="/index.php?title=File:Beat_Cadence.png" title="File:Beat Cadence.png">thumb</a> == Introduction == The so called Internet of Things (IoT) is expected to consist of multiple Billion devices by 2020. In such a projection onl..."</p>
<p><b>New page</b></p><div>[[File:Beat_Cadence.png|thumb]]<br />
<br />
== Introduction ==<br />
The so called Internet of Things (IoT) is expected to consist of multiple Billion devices by 2020. In such a projection only low-cost and low-power devices are sustainable. To this end, the Integrated System Laboratory (IIS) is together with the industry partner Advanced Circuit Pursuit (ACP) developing a highly integrated SoC for the IoT in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost as well as power consumption show room for improvement.<br />
<br />
== Project Description==<br />
The goal of this project is to thoroughly analyze an important block in the targeted IoT SoC responsible for synchronization and repetition combining which is currently written using a High Level Synthesis (HLS) approach with Cadence tools. But, a hand-engineered digital architecture is expected to integrate the same functionality occupying less area and consume less power. Therefore, the HLS block will be redesigned using VHDL. Depending on the students interest an ASIC design can be targeted or an FPGA platform can be used for fast prototyping using e.g. the [[evalEDGE]] platform. This project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a machine.<br />
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===Status: Available ===<br />
: Looking for 1-2 Semester students<br />
: Contact: [[:User:Weberbe|Benjamin Weber]]<br />
<br />
===Prerequisites===<br />
: Interest in Digital Design or Communications<br />
: VLSI I is plus<br />
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===Character===<br />
: 10% Theory, Algorithms and Simulation<br />
: 70% Implementation (HLS/VHDL)<br />
: 20% ASIC Implementation / FPGA Integration<br />
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===Professor===<br />
[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]<br />
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[[Category:Digital]]<br />
[[Category:ASIC]]<br />
[[Category:FPGA]]<br />
[[Category:Telecommunications]]<br />
[[Category:Available]]<br />
[[Category:Hot]]<br />
[[Category:Semester Thesis]]<br />
[[Category:Weberbe]]</div>
Weberbe