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Beat DigRF

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Short Description

Emerging applications for the Internet-of-Things (IoT) always require some type of communication interface with the rest of the world. Due to its ubiquitous coverage, the 2G cellular standard GSM and its enhancements are good candidates for the communication interface. Whenever a power plug is not an option ultra long battery life is a key requirement. And, as the number of IoT nodes increases ultra low cost per node is yet another requirement. In order to comply with IoT node requirements high integration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) modems are used.

Bearing this in mind, a single chip Physical Layer (PHY) has been developed at the institute in the stoneEDGE project. It combines a commercially available RF IC from ACP AG [1] and Digital Baseband (DBB) developed at the institute. The RF and DBB portions of stoneEDGE communicate using the standardized DigRF 1.12 interface [2]. However, the DigRF standard is by definition the interface between an RF IC and a DBB IC. Hence, it is an off-chip interface and by no means intended for on-chip use.

The goal of this project is to thoroughly analyze the DigRF interface implemented in the stoneEDGE project and replace it with an on-chip suitable solution. The found solution must outperform the existing DigRF implementation in terms of power consumption and area requirements. This project provides a good opportunity to dig deep into an existing design and hopefully give reason to refrain from using off-chip interfaces for on-chip communication.

Status: Obsolete

Supervision: Benjamin Weber


[1] Advanced Circuit Pursuit, ACP AG., September 2015.

[2] DigRF BASEBAND / RF DIGITAL INTERFACE SPECIFICATION - Logical, Electrical and Timing Characteristics - EGPRS Version., September 2015.