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CLIC for the CVA6

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Status: Available


CVA6 (formerly Ariane) is a 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and industry. The CVA6 is currently using a basic interrupt controller (often called CLINT) to handle timer, external and software interrupts. This interrupt controller is designed for generic UNIX workloads, but fails to deliver when interrupt latency, interrupt nesting and fine grained control over interrupt priorities/levels is more critical. A new specification outlines The Core-Local Interrupt Controller (CLIC)[2] promising low-latency, vectored, pre-emptive interrupts that tries to fill this gap.


The goal of this project is to take the already existing CLIC IP developed at IIS, integrate it with the CVA6 and explore extensions to facilitate virtualization and guarantee security properties. The IP itself is only part of the puzzle: On the core side various new Control and Status registers (CSRs) need to be implemented, the interrupt interface needs to be overhauled (level sensitive interrupts versus handshake interface) and core internal logic needs to be adapted to handle interrupt levels, selective hardware vectoring and more.

CVA6 also has experimental support for the RISC-V Hypervisor extension [3] allowing and facilitating virtualization of guest operating systems. Investigate how the CLIC interacts with the Hypervisor extension and propose and implement new extensions to the CLIC that facilitate/accelerate virtualization (i.e. reducing the amount of times the hypervisor has to intervene). Inspiration can be drawn from the RISC-V Advanced Interrupt Architecture (AIA) [4] working group tries to solve similar problems.

On the software side Linux can be extended to support the CLIC and potential custom extensions.


  • 20% Literature / architecture review
  • 40% RTL implementation
  • 20% Bare-metal C programming
  • 20% Evaluation


  • Strong interest in computer architecture
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with low-level programming


[1] CVA6: CVA6 RISC-V CPU (GitHub repository)

[2] RISC-V Core-Local Interrupt Controller (CLIC) (GitHub repository)

[3] RISC-V Instruction Set Manual (GitHub repository)

[4] RISC-V Advanced Interrupt Architecture (AIA) (GitHub repository)