Category:ASIC
From iis-projects
In an ASIC (Application Specific Integrated Circuit) project you will be working on the design of an integrated circuit. This will include:
- Researching different architectures to find the most suitable one for the project
- Designing the system architecture
- Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for digital projects, and schematic entry for analog projects.
- Running simulations to verify the correct functionality and ensuring that the specifications of the circuit are met
- The actual physical design of the integrated circuit
- Verifications to make sure that the circuit can be properly manufactured
- Providing documentation for the test and use of the integrated circuit
Depending on the project, your design may be sent for manufacturing to be used in future projects.
Pages in category "ASIC"
The following 93 pages are in this category, out of 93 total.
A
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- Accelerator for Spatio-Temporal Video Filtering
- Advanced 5G Repetition Combining
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
C
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Compressed Sensing for Wireless Biosignal Monitoring
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- CPS Software-Configurable State-Machine
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a HDMI Video Interface for PULP
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
D
- Deep Learning for Brain-Computer Interface
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of a Fused Multiply Add Floating Point Unit
- Design of a VLIW processor architecture based on RISC-V
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Digital Beamforming for Ultrasound Imaging
- DMA Streaming Co-processor
E
H
L
M
N
P
R
S
- Sandro Belfanti
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Shared Correlation Accelerator for an RF SoC
- Signal to Noise Ratio Estimation for 3G standards
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spiking Neural Network for Autonomous Navigation
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- User:Susman