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Latest revision as of 11:10, 9 February 2015
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Pages in category "Completed"
The following 200 pages are in this category, out of 282 total.
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- A computational memory unit using phase-change memory devices
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Recurrent Neural Network Speech Recognition Chip
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Trustworthy Three-Factor Authentication System
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for HPC monitoring
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Aliasing-Free Wavetable Music Synthesizer
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autonomous Sensing For Trains In The IoT Era
B
- Bandwidth Efficient NEureka
- Baseband Meets CPU
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
C
- Cell-Free mmWave Massive MIMO Communication
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation for TD-HSPA
- Charging System for Implantable Electronics
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Compressed Sensing Reconstruction on FPGA
- Compression of Ultrasound data on FPGA
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a HDMI Video Interface for PULP
D
- Data Mapping for Unreliable Memories
- DC-DC Buck converter in 65nm CMOS
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning for Brain-Computer Interface
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of combined Ultrasound and Electromyography systems
- Design of low-offset dynamic comparators
- Design of MEMs Sensor Interface
- Designing a Power Management Unit for PULP SoCs
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of a Rockfall Sensor Node
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Transmitter for Mobile Communications
E
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Synchronization of Manycore Systems (M/1S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating SoA Post-Training Quantization Algorithms
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploring Algorithms for Early Seizure Detection
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA-Based Digital Frontend for 3G Receivers
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware/software co-programming on the Parallella platform
- HERO: TLB Invalidation
- High Performance Cellular Receivers in Very Advanced CMOS
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Throughput Turbo Decoder Design
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Resolution, Calibrated Folding ADCs
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Indoor Positioning with Bluetooth
- Inductive Charging Circuit for Implantable Devices
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- Learning Image Decompression with Convolutional Networks
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Temperature-insensitive Timer
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- MatPHY: An Open-Source Physical Layer Development Framework
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Multi issue OoO Ariane Backend (M)
- Multi-Band Receiver Design for LTE Mobile Communication
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Next Generation Synchronization Signals
- NORX - an AEAD algorithm for the CAESAR competition
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- NVDLA meets PULP
O
- Online Learning of User Features (1S)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Outdoor Precision Object Tracking for Rockfall Experiments
