Difference between revisions of "Category:Completed"
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Latest revision as of 10:10, 9 February 2015
Redirect to:
Pages in category "Completed"
The following 200 pages are in this category, out of 282 total.
(previous page) (next page)D
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of combined Ultrasound and Electromyography systems
- Design of low-offset dynamic comparators
- Design of MEMs Sensor Interface
- Designing a Power Management Unit for PULP SoCs
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of a Rockfall Sensor Node
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Transmitter for Mobile Communications
E
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Synchronization of Manycore Systems (M/1S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating SoA Post-Training Quantization Algorithms
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploring Algorithms for Early Seizure Detection
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA-Based Digital Frontend for 3G Receivers
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware/software co-programming on the Parallella platform
- HERO: TLB Invalidation
- High Performance Cellular Receivers in Very Advanced CMOS
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Throughput Turbo Decoder Design
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Resolution, Calibrated Folding ADCs
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Indoor Positioning with Bluetooth
- Inductive Charging Circuit for Implantable Devices
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- Learning Image Decompression with Convolutional Networks
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Temperature-insensitive Timer
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- MatPHY: An Open-Source Physical Layer Development Framework
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Multi issue OoO Ariane Backend (M)
- Multi-Band Receiver Design for LTE Mobile Communication
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Next Generation Synchronization Signals
- NORX - an AEAD algorithm for the CAESAR competition
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- NVDLA meets PULP
O
- Online Learning of User Features (1S)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Outdoor Precision Object Tracking for Rockfall Experiments
P
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Precise Ultra-low-power Timer
- Predictable Execution on GPU Caches
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
R
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Optical Flow Using Neural Networks
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Reconfigurability of SHA-3 candidates
- Resource Partitioning of Caches
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Running Rust on PULP
S
- Scattering Networks for Scene Labeling
- SCMI Support for Power Controller Subsystem
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Shared Correlation Accelerator for an RF SoC
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Smart e-glasses for concealed recording of EEG signals
- Smart Meters
- Smart Virtual Memory Sharing
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Successive Interference Cancellation for 3G Downlink
- Switched Capacitor Based Bandgap-Reference
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
T
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Timing Channel Mitigations for RISC-V Cores
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards Autonomous Navigation for Nano-Blimps
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT