Difference between revisions of "Category:Completed"
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==Digital== | ==Digital== | ||
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| + | category = Completed | ||
| + | category = Digital | ||
| + | category = 2015 | ||
| + | </DynamicPageList> | ||
| + | ===2014=== | ||
| + | <DynamicPageList> | ||
| + | category = Completed | ||
| + | category = Digital | ||
| + | category = 2014 | ||
| + | </DynamicPageList> | ||
===2013=== | ===2013=== | ||
<DynamicPageList> | <DynamicPageList> | ||
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category = 2013 | category = 2013 | ||
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==Nano TCAD== | ==Nano TCAD== | ||
Revision as of 10:58, 9 February 2015
These projects have already been completed. You can take a look at the results of the project and learn more.
Digital
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
Nano TCAD
2013
No pages meet these criteria.
Pages in category "Completed"
The following 22 pages are in this category, out of 282 total.
(previous page) (next page)T
U
- Ultra low power wearable ultrasound probe
- Ultra Low-Power Oscillator
- Ultra-low power processor design
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound based hand gesture recognition
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
