Category:Completed
From iis-projects
These projects have already been completed. You can take a look at the results of the project and learn more.
Digital
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
Nano TCAD
2013
No pages meet these criteria.
Pages in category "Completed"
The following 200 pages are in this category, out of 210 total.
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- A computational memory unit using phase-change memory devices
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Recurrent Neural Network Speech Recognition Chip
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Trustworthy Three-Factor Authentication System
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for HPC monitoring
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
B
C
- Cell-Free mmWave Massive MIMO Communication
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation for TD-HSPA
- Charging System for Implantable Electronics
- CMOS power amplifier for field measurements in MRI systems
- Compressed Sensing Reconstruction on FPGA
- Compression of Ultrasound data on FPGA
- Creating a HDMI Video Interface for PULP
D
- Data Mapping for Unreliable Memories
- DC-DC Buck converter in 65nm CMOS
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning for Brain-Computer Interface
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of low-offset dynamic comparators
- Development of a Rockfall Sensor Node
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Transmitter for Mobile Communications
E
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploring Algorithms for Early Seizure Detection
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Fluffy bunny project
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA-Based Digital Frontend for 3G Receivers
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware/software co-programming on the Parallella platform
- HERO: TLB Invalidation
- High Performance Cellular Receivers in Very Advanced CMOS
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Throughput Turbo Decoder Design
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Resolution, Calibrated Folding ADCs
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing Hibernation on the ARM Cortex M0
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Indoor Positioning with Bluetooth
- Inductive Charging Circuit for Implantable Devices
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- Learning Image Decompression with Convolutional Networks
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Temperature-insensitive Timer
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Manycore System on FPGA (M/S/G)
- MatPHY: An Open-Source Physical Layer Development Framework
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Multi issue OoO Ariane Backend (M)
- Multi-Band Receiver Design for LTE Mobile Communication
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Next Generation Synchronization Signals
- NORX - an AEAD algorithm for the CAESAR competition
- NVDLA meets PULP
P
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Predictable Execution on GPU Caches
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
R
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Optical Flow Using Neural Networks
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Reconfigurability of SHA-3 candidates
S
- Scattering Networks for Scene Labeling
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Shared Correlation Accelerator for an RF SoC
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Smart Virtual Memory Sharing
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Spatio-Temporal Video Filtering
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Successive Interference Cancellation for 3G Downlink
- Switched Capacitor Based Bandgap-Reference
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
T
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Timing Channel Mitigations for RISC-V Cores
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards Autonomous Navigation for Nano-Blimps
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
