Category:Completed
From iis-projects
These projects have already been completed. You can take a look at the results of the project and learn more.
Contents
Analog
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
2012
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
Digital
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
Nano Electronics
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
No pages meet these criteria.
2012
No pages meet these criteria.
Nano TCAD
2015
No pages meet these criteria.
2014
No pages meet these criteria.
2013
No pages meet these criteria.
2012
No pages meet these criteria.
Pages in category "Completed"
The following 200 pages are in this category, out of 258 total.
(previous page) (next page)A
- A computational memory unit using phase-change memory devices
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Recurrent Neural Network Speech Recognition Chip
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Trustworthy Three-Factor Authentication System
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for HPC monitoring
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Aliasing-Free Wavetable Music Synthesizer
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autonomous Sensing For Trains In The IoT Era
B
- Baseband Meets CPU
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
C
- Cell-Free mmWave Massive MIMO Communication
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation for TD-HSPA
- Charging System for Implantable Electronics
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Compressed Sensing Reconstruction on FPGA
- Compression of Ultrasound data on FPGA
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a HDMI Video Interface for PULP
D
- Data Mapping for Unreliable Memories
- DC-DC Buck converter in 65nm CMOS
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning for Brain-Computer Interface
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of combined Ultrasound and Electromyography systems
- Design of low-offset dynamic comparators
- Design of MEMs Sensor Interface
- Designing a Power Management Unit for PULP SoCs
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of a Rockfall Sensor Node
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Transmitter for Mobile Communications
E
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Synchronization of Manycore Systems (M/1S)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating SoA Post-Training Quantization Algorithms
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploring Algorithms for Early Seizure Detection
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA-Based Digital Frontend for 3G Receivers
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware/software co-programming on the Parallella platform
- HERO: TLB Invalidation
- High Performance Cellular Receivers in Very Advanced CMOS
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- High Throughput Turbo Decoder Design
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Resolution, Calibrated Folding ADCs
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Indoor Positioning with Bluetooth
- Inductive Charging Circuit for Implantable Devices
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- Learning Image Decompression with Convolutional Networks
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Temperature-insensitive Timer
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- MatPHY: An Open-Source Physical Layer Development Framework
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Multi issue OoO Ariane Backend (M)
- Multi-Band Receiver Design for LTE Mobile Communication
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Next Generation Synchronization Signals
- NORX - an AEAD algorithm for the CAESAR competition
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- NVDLA meets PULP
O
P
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Precise Ultra-low-power Timer
- Predictable Execution on GPU Caches
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
R
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Optical Flow Using Neural Networks
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Reconfigurability of SHA-3 candidates
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Running Rust on PULP
