Category:Hot
From iis-projects
These projects are hot because we believe that they will lead to interesting results which we expect will have an impact on our research. The probability of being part of a publication is higher in these projects.
Pages in category "Hot"
The following 191 pages are in this category, out of 191 total.
A
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System To Control Phone And Electronic Device Without Hands
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Advanced EEG glasses
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- ASIC Development of 5G-NR LDPC Decoder
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Sensors for IoT
B
- Bandwidth Efficient NEureka
- BCI-controlled Drone
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- BigPULP: Multicluster Synchronization Extensions
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
C
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge and heat transport through graphene nanoribbon based devices
- CLIC for the CVA6
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compression of iEEG Data
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Creating a HDMI Video Interface for PULP
D
- Data Augmentation Techniques in Biosignal Classification
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep neural networks for seizure detection
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of low mismatch DAC used for VAD
- Design of MEMs Sensor Interface
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Designing a Power Management Unit for PULP SoCs
- Developing High Efficiency Batteries for Electric Cars
- Development of a syringe label reader for the neurocritical care unit
- Development of an efficient algorithm for quantum transport codes
- Development of an implantable Force sensor for orthopedic applications
- Development of statistics and contention monitoring unit for PULP
E
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN compression
- Efficient TNN Inference on PULP Systems
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient Serial Link
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploring NAS spaces with C-BRED
F
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Finite element modeling of electrochemical random access memory
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
G
H
- Hardware Constrained Neural Architechture Search
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Heroino: Design of the next CORE-V Microcontroller
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
- Huawei Research
I
- IBM Research
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing DSP Instructions in Banshee (1S)
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Integrated silicon photonic structures-Lumiphase
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- Learning at the Edge with Hardware-Aware Algorithms
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Low Latency Brain-Machine Interfaces
- Low-power Temperature-insensitive Timer
M
- Manycore System on FPGA (M/S/G)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Modular Distributed Data Collection Platform
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
N
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Recording Interface and Signal Processing
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Non-blocking Algorithms in Real-Time Operating Systems
- Novel Metastability Mitigation Technique
O
- Object Detection and Tracking on the Edge
- On - Device Continual Learning for Seizure Detection on GAP9
- On-chip clock synthesizer design and porting
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- Open Power-On Chip Controller Study and Integration
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
P
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Predict eye movement through brain activity
- Probing the limits of fake-quantised neural networks
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- PVT Dynamic Adaptation in PULPv3
Q
R
S
- Satellite Internet of Things
- SCMI Support for Power Controller Subsystem
- Self Aware Epilepsy Monitoring
- Shared Correlation Accelerator for an RF SoC
- Smart e-glasses for concealed recording of EEG signals
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Softmax for Transformers (M/1-2S)
- Spatio-Temporal Video Filtering
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Streaming Integer Extensions for Snitch (M/1-2S)
- System Emulation for AR and VR devices
T
- Ternary Neural Networks for Face Recognition
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Towards global Brain-Computer Interfaces
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
