Category:Master Thesis
From iis-projects
The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.
Pages in category "Master Thesis"
The following 200 pages are in this category, out of 329 total.
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- A computational memory unit using phase-change memory devices
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Advanced 5G Repetition Combining
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Ambient RF Energy harvesting for Wireless Sensor Network
- AMZ Driverless Competition Embedded Systems Projects
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- Analog building blocks for mmWave manipulation
- Analog Compute-in-Memory Accelerator Interface and Integration
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
B
- Baseband Meets CPU
- Bateryless Heart Rate Monitoring
- Battery indifferent wearable Ultrasound
- BCI-controlled Drone
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Biomedical Circuits, Systems, and Applications
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- BLISS - Battery-Less Identification System for Security
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
C
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing vs JPEG
- Compression of Ultrasound data on FPGA
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- CPS Software-Configurable State-Machine
- Creating a HDMI Video Interface for PULP
D
- Data Augmentation Techniques in Biosignal Classification
- Deep Learning for Brain-Computer Interface
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design and Implementation of ultra low power vision system
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a VLIW processor architecture based on RISC-V
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of an Ultra-Reliable Low-Latency Modem
- Design of combined Ultrasound and Electromyography systems
- Design of MEMs Sensor Interface
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Designing a Power Management Unit for PULP SoCs
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing High Efficiency Batteries for Electric Cars
- Development of an efficient algorithm for quantum transport codes
- Development of an implantable Force sensor for orthopedic applications
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Front End Design & Frequency Offset Estimation for V2X Communications
- DMA Streaming Co-processor
E
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Neutral Multi Sensors Wearable Device
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Extend the RI5CY core with priviledge extensions
- Extending the RISCV backend of LLVM to support PULP Extensions
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fast Accelerator Context Switch for PULP
- Fast Wakeup From Deep Sleep State
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finite element modeling of electrochemical random access memory
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- Fluffy bunny project
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
G
H
- Hardware Accelerated Derivative Pricing
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware/software co-programming on the Parallella platform
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Heroino: Design of the next CORE-V Microcontroller
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-Performance & V2X Cellular Communications
- High-Speed Channel Estimation & Tracking for V2X Communications
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Channel Coding & Decoding for V2X Communications
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Huawei Research
- Human Intranet
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- IBM Research
- Image and Video Processing
- Implementation of a NB-IoT Positioning System
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Integrated silicon photonic structures-Lumiphase
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Internet of Things Network Synchronizer
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
