Category:Tbenz
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Pages in category "Tbenz"
The following 42 pages are in this category, out of 42 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced Data Movers for Modern Neural Networks
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
C
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
D
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
E
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
F
I
T
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
