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Channel Decoding for TD-HSPA

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Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.




Christoph Roth


Hasler Foundation
ETH Zurich




In order to deliver high data rates and good quality of service, required to serve the ever-increasing number of mobile users, modern mobile cellular communication standards rely on high-performance error-correction schemes. Along with the well-established convolutional codes, turbo coding has been considered in many recent standards, including the 3GPP standard suite. In addition to this strong class of channel codes, the HSPA evolution of 3GPP further specifies the use of hybrid-ARQ, which allows for rapid retransmission of erroneously received data packets. This key feature is a crucial mechanism to adapt to rapidly varying mobile channel conditions and, thus, enables mobile terminals to maintain high average data rates.

In this work, we have continued our efforts to integrate the channel decoding chain for 3GPP TD-HSPA in dedicated hardware. In the first part of the project, a standard-compliant model of the decoding chain has been implemented in MATLAB, including the hybrid-ARQ functionality. In the second part, a high-level VLSI architecture for the decoding chain has been devised and prototypes for the turbo decoder and Viterbi decoder implemented in silicon. The main challenge concerning the integration of the channel decoders has been to implement area- and power-efficient solutions that operate close-to-optimum for all (possibly high) code rates foreseen by the standard.

This decoding chain will be part of a digital receiver baseband for TD-HSPA, currently being integrated at the IIS.


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