View source for Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS

[[File:PLL.png|600px|thumb|right|Typical Charge-Pump PLL]]

==Short Description==
In order to complete the transceiver which is part of a project aiming at correcting the motion in Magnetic Resonance Imaging, a Phase-Locked Loop (PLL) is needed to supply the clock to an Analog-to-Digital Converter (ADC). In order to have a better rejection of undesired signals, the reference clock available on the custom IC needs to be adapted to a higher frequency.

The first part of the project will consist in designing a ring-oscillator based Voltage-Controlled Oscillator (VCO) which is the milestone to realize a complete PLL. Afterwards, the design of several other blocks will have to supplement this VCO: Phase Frequency Detector (PFD), Charge Pump, Loop Filter and Divider.

The goal of this project is therefore to design a power efficient PLL with a low integrated jitter.

===Status: Available ===
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s)
: Contact: [[:User:Mocquard | Guillaume Mocquard]], [[:User:Burger | Thomas Burger]]

===Prerequisites===
: Analog Integrated Circuits (AIC)

===Character===
: 30% Theory
: 70% Circuit Design

===Professor===
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->

[[#top|↑ top]]
==Detailed Task Description==

===Goals===
===Practical Details===
* '''[[Project Plan]]'''
* '''[[Project Meetings]]'''
* '''[[Design Review]]'''
* '''[[Coding Guidelines]]'''
* '''[[Final Report]]'''
* '''[[Final Presentation]]'''

==Results== 

==Links== 
[[Category:Analog]]
[[Category:Available]]
[[Category:Bachelor Thesis]]
[[Category:Semester Thesis]]
[[Category:Burger]]
[[Category:Mocquard]]
[[Category:Analog IC Design]]
[[#top|↑ top]]