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Difference between revisions of "Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS"

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[[Category:Bachelor Thesis]]
[[Category:Bachelor Thesis]]
[[Category:Semester Thesis]]
[[Category:Semester Thesis]]
[[Category:Analog IC Design]]
[[Category:Analog IC Design]]
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[[#top|↑ top]]

Latest revision as of 16:49, 27 January 2021

Typical Charge-Pump PLL

Short Description

In order to complete the transceiver which is part of a project aiming at correcting the motion in Magnetic Resonance Imaging, a Phase-Locked Loop (PLL) is needed to supply the clock to an Analog-to-Digital Converter (ADC). In order to have a better rejection of undesired signals, the reference clock available on the custom IC needs to be adapted to a higher frequency.

The first part of the project will consist in designing a ring-oscillator based Voltage-Controlled Oscillator (VCO) which is the milestone to realize a complete PLL. Afterwards, the design of several other blocks will have to supplement this VCO: Phase Frequency Detector (PFD), Charge Pump, Loop Filter and Divider.

The goal of this project is therefore to design a power efficient PLL with a low integrated jitter.

Status: Available

Type: Bachelor's Thesis or Semester Project for 1-2 student(s)
Contact: Guillaume Mocquard, Thomas Burger


Analog Integrated Circuits (AIC)


30% Theory
70% Circuit Design


Qiuting Huang

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Detailed Task Description


Practical Details



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