Difference between revisions of "Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS"
From iis-projects
(Created page with "==Short Description== In order to complete the transceiver which is part of a project aiming at correcting the motion in Magnetic Resonance Imaging, a Phase-Locked Loop (PLL)...") |
|||
| Line 8: | Line 8: | ||
===Status: Available === | ===Status: Available === | ||
: Type: Bachelor's Thesis or Semester Project for 1-2 student(s) | : Type: Bachelor's Thesis or Semester Project for 1-2 student(s) | ||
| − | : Contact: [[:User:Mocquard | Guillaume Mocquard]] | + | : Contact: [[:User:Mocquard | Guillaume Mocquard]], [[:User:Burger | Thomas Burger]] |
===Prerequisites=== | ===Prerequisites=== | ||
Revision as of 14:56, 22 January 2021
Contents
Short Description
In order to complete the transceiver which is part of a project aiming at correcting the motion in Magnetic Resonance Imaging, a Phase-Locked Loop (PLL) is needed to supply the clock to an Analog-to-Digital Converter (ADC). In order to have a better rejection of undesired signals, the reference clock available on the custom IC needs to be adapted to a higher frequency.
The first part of the project will consist in designing a ring-oscillator based Voltage-Controlled Oscillator (VCO) which is the milestone to realize a complete PLL. Afterwards, the design of several other blocks will have to supplement this VCO: Phase Frequency Detector (PFD), Charge Pump, Loop Filter and Divider.
The goal of this project is therefore to design a power efficient PLL with a low integrated jitter.
Status: Available
- Type: Bachelor's Thesis or Semester Project for 1-2 student(s)
- Contact: Guillaume Mocquard, Thomas Burger
Prerequisites
- Analog Integrated Circuits (AIC)
Character
- 30% Theory
- 70% Circuit Design
