|
|
| Line 1: |
Line 1: |
| − | [[Category:Digital]] | + | #REDIRECT [[Editing Coherence-Capable Write-Back L1 Data Cache for Ariane (M)]] |
| − | [[Category:High Performance SoCs]]
| |
| − | [[Category:Computer Architecture]]
| |
| − | [[Category:2020]]
| |
| − | [[Category:Master Thesis]]
| |
| − | [[Category:Semester Thesis]]
| |
| − | [[Category:Nwistoff]]
| |
| − | [[Category:Zarubaf]]
| |
| − | [[Category:Available]]
| |
| − | | |
| − | | |
| − | == Introduction ==
| |
| − | | |
| − | Ariane is an open-source, 6-stage, 64-bit, in-order RISC-V core developed at IIS [1]. It is capable of booting Linux and it is widely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory contents to accelerate future accesses to this data.
| |
| − | | |
| − | To increase a system's performance on parallel workloads, a common technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of the (partial) main memory in its respective L1 data cache. Working of different copies of the same data can quickly result in inconsistencies between the cores' memory views.
| |
| − | | |
| − | This challenge can be tackled by introducing ''cache-coherence'', a set of mechanisms that keep the local caches synchronized and up-to-date.
| |
| − | | |
| − | == Project ==
| |
| − | | |
| − | The goal of this project is to implement general coherence support in Ariane’s write-back L1 data cache, so that it can be integrated into various coherent memory systems. For instance,
| |
| − | * the cache needs to track and handle additional state of the cache lines, e.g. whether they are unique or shared, and
| |
| − | * a coherent memory system must be able to invalidate or update specific cache lines, and to request specific cache lines for forwarding or write-back.
| |
| − | | |
| − | Depending on the work’s progress, this functionality can be demonstrated by implementing adapters to existing coherent interconnects, such as OpenPiton’s NoCs [2,3], BlackParrot’s BedRock [4], or SiFive’s TileLink [5] and thus building a sample multi-core system.
| |
| − | | |
| − | ===== Requirements =====
| |
| − | | |
| − | * Strong interest in computer architecture
| |
| − | * Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I
| |
| − | * Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II
| |
| − | | |
| − | Composition: 30% Architecture specification, 40% Verification, 30% RTL Implementation
| |
| − | | |
| − | ===== Project Supervisors =====
| |
| − | * [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]
| |
| − | * [[:User:Zarubaf | Florian Zaruba]]: [mailto:zarubaf@iis.ee.ethz.ch zarubaf@iis.ee.ethz.ch]
| |
| − | | |
| − | == References ==
| |
| − | | |
| − | * [1] https://github.com/openhwgroup/cva6
| |
| − | * [2] http://parallel.princeton.edu/papers/openpiton-asplos16.pdf
| |
| − | * [3] http://www.parallel.princeton.edu/papers/aspl20-balkind.pdf
| |
| − | * [4] https://github.com/black-parrot/black-parrot/blob/master/docs/bedrock_guide.md
| |
| − | * [5] https://sifive.cdn.prismic.io/sifive%2Fcab05224-2df1-4af8-adee-8d9cba3378cd_tilelink-spec-1.8.0.pdf
| |
