Difference between revisions of "Completed"
From iis-projects
(→2021) |
(→Digital) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 52: | Line 52: | ||
</DynamicPageList> | </DynamicPageList> | ||
| − | ==Digital== | + | ==Digital== |
| + | |||
| + | ===2023=== | ||
| + | <DynamicPageList> | ||
| + | suppresserrors = true | ||
| + | category = Completed | ||
| + | category = Digital | ||
| + | category = 2023 | ||
| + | </DynamicPageList> | ||
| + | |||
| + | |||
| + | ===2022=== | ||
| + | <DynamicPageList> | ||
| + | suppresserrors = true | ||
| + | category = Completed | ||
| + | category = Digital | ||
| + | category = 2022 | ||
| + | </DynamicPageList> | ||
| + | |||
| + | |||
===2021=== | ===2021=== | ||
<DynamicPageList> | <DynamicPageList> | ||
Latest revision as of 19:43, 12 January 2023
These projects have already been completed. You can take a look at the results of the project and learn more.
Contents
Analog
2021
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Low-Dropout Regulators for Magnetic Resonance Imaging
- DC-DC Buck converter in 65nm CMOS
2017
2016
- Switched Capacitor Based Bandgap-Reference
- High performance continous-time Delta-Sigma ADC for biomedical applications
- GUI-developement for an action-cam-based eye tracking device
2015
2014
2013
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
2012
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
Digital
2023
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Enabling Efficient Systolic Execution on MemPool (M)
- Network-off-Chip (M)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Transformer Deployment on Heterogeneous Many-Core Systems
- Smart Meters
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
2022
- Bandwidth Efficient NEureka
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Resource Partitioning of Caches
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Enabling Efficient Systolic Execution on MemPool (M)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Evaluating SoA Post-Training Quantization Algorithms
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Wireless EEG Acquisition and Processing
- Development of statistics and contention monitoring unit for PULP
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Implementing DSP Instructions in Banshee (1S)
- Design of combined Ultrasound and Electromyography systems
- Designing a Power Management Unit for PULP SoCs
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Ultrasound signal processing acceleration with CUDA
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
2021
- Novel Metastability Mitigation Technique
- Analog Compute-in-Memory Accelerator Interface and Integration
- Wearables in Fashion
- Outdoor Precision Object Tracking for Rockfall Experiments
- Autonomous Sensing For Trains In The IoT Era
- CLIC for the CVA6
- Online Learning of User Features (1S)
- Feature Extraction for Speech Recognition (1S)
- SCMI Support for Power Controller Subsystem
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Implementing DSP Instructions in Banshee (1S)
- Streaming Integer Extensions for Snitch (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Next Generation Synchronization Signals
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Ultra low power wearable ultrasound probe
- Machine Learning for extracting Muscle features using Ultrasound 2
- Hardware Constrained Neural Architechture Search
- Implementation of an AES Hardware Processing Engine (B/S)
- Transforming MemPool into a CGRA (M)
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Machine Learning for extracting Muscle features using Ultrasound
- Compression of Ultrasound data on FPGA
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- Time Gain Compensation for Ultrasound Imaging
2020
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Hypervisor Extension for Ariane (M)
- Advanced 5G Repetition Combining
- Multi issue OoO Ariane Backend (M)
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Low Latency Brain-Machine Interfaces
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- Deep Convolutional Autoencoder for iEEG Signals
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Timing Channel Mitigations for RISC-V Cores
2019
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Floating-Point Divide & Square Root Unit for Transprecision
- TCNs vs. LSTMs for Embedded Platforms
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Exploring Algorithms for Early Seizure Detection
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Indoor Positioning with Bluetooth
- Improving Resiliency of Hyperdimensional Computing
- Toward Superposition of Brain-Computer Interface Models
- LightProbe - WIFI extension (PCB)
2018
- Digital Audio Interface for Smart Intensive Computing Triggering
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Creating a HDMI Video Interface for PULP
- Interference Cancellation for EC-GSM-IoT
2017
- A computational memory unit using phase-change memory devices
- Deep Learning for Brain-Computer Interface
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Turbo Equalization for Cellular IoT
- Sensor Fusion for Rockfall Sensor Node
- Development of a Rockfall Sensor Node
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- A Wireless Sensor Network for a Smart Building Monitor and Control
- BigPULP: Multicluster Synchronization Extensions
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
2016
- A Recurrent Neural Network Speech Recognition Chip
- Efficient NB-IoT Uplink Design
- Internet of Things Network Synchronizer
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- High-speed Scene Labeling on FPGA
- Learning Image Decompression with Convolutional Networks
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- Implementing Hibernation on the ARM Cortex M0
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Spatio-Temporal Video Filtering
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
2015
- Hardware Accelerated Derivative Pricing
- Glitches Reduce Listening Time of Your iPod
- FFT-based Convolutional Network Accelerator
- Real-Time Optical Flow Using Neural Networks
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- Active-Set QP Solver on FPGA
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Hardware/software co-programming on the Parallella platform
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Real-Time Stereo to Multiview Conversion
2014
- EvalEDGE: A 2G Cellular Transceiver FMC
- Real-Time Stereo to Multiview Conversion
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of an Approximate Floating Point Unit
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
Nano Electronics
2016
2015
2014
2013
2012
